Abstract
This chapter discusses methods for circuit-level optimization. We discuss a methodology for generating the optimal energy-delay tradeoff by tuning gate size and supply and threshold voltages. The methodology is based on the sensitivity approach to measure and balance the benefits of all the tuning variables. The analysis will be illustrated on datapath logic, and the results will serve as a guideline for architecture-level design in later chapters.
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References
References
Stojanović V et al (2002) "Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization," in Proc. Eur. Solid-State Circuits Conf, Sept, pp 211–214
Marković D et al (Aug. 2004) "Methods for True Energy-Performance Optimization," IEEE J. Solid-State Circuits 39(8):1282–1293
S. Ma and P. Franzon, "Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers," IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 1150-1153, Sept. 1994.
Additional References
Gonzalez R, Gordon B, Horowitz MA (Aug. 1997) "Supply and Threshold Voltage Scaling for Low Power CMOS," IEEE J. Solid-State Circuits 32(8):1210–1216
Zyuban V et al (Aug. 2004) "Integrated Analysis of Power and Performance for Pipelined Microprocessors," IEEE Trans. Computers 53(8):1004–1016
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© 2012 Springer Science+Business Media New York
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Marković, D., Brodersen, R.W., Nikolić, B. (2012). Circuit Optimization. In: DSP Architecture Design Essentials. Electrical Engineering Essentials. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-9660-2_2
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DOI: https://doi.org/10.1007/978-1-4419-9660-2_2
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