Electrical Design of Through Silicon Via

1. Front Matter

   Pages i-ix

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2. Introduction

   • Jun So Pak, Joungho Kim

   Pages 1-21

3. Electrical Modeling of a Through Silicon Via

   • Joohee Kim, Jun So Pak, Joungho Kim

   Pages 23-60

4. High-Speed TSV-Based Channel Modeling and Design

   • Heegon Kim, Jun So Pak, Joungho Kim

   Pages 61-114

5. Noise Coupling and Shielding in 3D ICs

   • Jonghyun Cho, Jun So Pak, Joungho Kim

   Pages 115-146

6. Thermal Effects on TSV Signal Integrity

   • Manho Lee, Jun So Pak, Joungho Kim

   Pages 147-172

7. Power Distribution Network Modeling and Analysis for TSV and Interposer-Based 3D ICs in the Frequency Domain

   • Kiyeong Kim, Jun So Pak, Joungho Kim

   Pages 173-224

8. TSV Decoupling Schemes

   • Eunseok Song, Jun So Pak, Joungho Kim

   Pages 225-272

9. Back Matter

   Pages 273-280

   PDF

Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep into TSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered.

• 3-Dimensional Integrated Circuit Design
• Clock Distribution Networks
• High Speed IC Design
• Noise Coupling
• On-Chip Decoupling
• Power Distribution Networks
• Power Integrity
• Signal Integrity
• Thermal Effects
• Through Silicon Via (TSV)

• Electrical Engineering, KAIST, Daejeon, Korea, Republic of (South Korea)

  Manho Lee

• System LSI, Samsung Electronics Co., Ltd, Hwaseong, Korea, Republic of (South Korea)

  Jun So Pak

• Electrical Engineering, Department Chair, KAIST, Daejeon, Korea, Republic of (South Korea)

  Joungho Kim

Manho Lee received the B.S. and M.S. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 2010 and 2012, respectively, where he is currently pursuing the Ph.D. degree in electrical engineering.

His current research interests include the modeling of noise coupling between active circuit and TSV.

Jun So Pak (M'02) received the B.S. degree in electrical communication engineering from Hanyang University, Seoul, Korea, in 1998 and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2000 and 2005, respectively.

He was a Research Fellow with the High Density Interconnection Group, National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan, in 2005, where he was involved in development of interconnection techniques and interposers for 3-D multichip packaging. Since 2007, he has been a Research Professor with the Department of Electrical Engineering, KAIST. He was the Founder and Director of the 3D-IC Research Center (3DIC- RC) in 2005. His current research interests include development of 3-D stacked chip packaging using through silicon via.

Dr. Pak was a recipient of the Research Fellowship Award from the Japan Society for the Promotion of Science in 2005.

Joungho Kim (M'04) received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively and the Ph.D. degree from the University of Michigan, Ann Arbor, in 1993, all in electrical engineering. He was involved in femtosecond time-domain optical measurement techniques for high-speed devices and circuit testing during his graduate study.

After completing the Ph.D. degree, he joined Picometrix, Inc., Ann Arbor, MI, in 1993, as a Research Engineer, where he was involved in development of pico-second sampling systems and 70-GHz photoreceivers. He joined theMemory Di-vision, Samsung Electronics, Kiheung, Korea, in 1994, where he was engaged in Gbit-scale dynamic random access memory design. He joined the Korea Advanced Institute of Science and Technology (KAIST), Taejon, Korea, in 1996, where he is currently a Professor with the Electrical Engineering and Computer Science Department. At KAIST, his research focuses on modeling, design and measurement methodologies of hierarchical semiconductor systems including high-speed chips, packages, interconnection and multilayer printed circuit boards. Specifically, his major research is focused on chip-package co-design and simulation for signal integrity, power integrity, ground integrity, timing integrity and radiated emission in 3-D semiconductor packages, system-in-packages (SiPs) and system-on-packages. He has successfully demonstrated low-noise and high-performance designs of more than ten SiPs for wireless communication applications, including ZigBee, T-DMB, NFC and UWB. He was on sabbatical leave with Silicon Image, Inc., Sunnyvale, CA, as a Staff Engineer, from 2001 to 2002. He was responsible for low-noise package design of SATA, FC, HDMI and Panel Link SerDes devices. Currently, he is the Director of the Satellite Research Laboratory, Hyundai Motors, Hwaseong-si, Kyungki-do, Korea, for electromagnetic interference and electromagnetic compatibility modeling of automotive RF, power electronic and cabling systems. He has authored or co-authored more than 210 papers in refereed journals and conferences.

Dr. Kim has been the Chair or the Co-Chair of the EDAPS Workshop since 2002. He is currently an Associate Editor of the IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY.

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