Overview
- Discusses high-level synthesis fundamentals.
- Presents a very comprehensive treatment on all aspects of power dissipation.
- Includes information on power reduction fundamentals, specifically peak power reduction, transient power reduction and leakage power reduction.
- Addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies.
- Deals primarily with high-level (architectural or behavioral) leakage.
- Contains an all-inclusive approach to power-driven high-level synthesis.
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Table of contents (10 chapters)
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Front Matter
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Back Matter
Keywords
About this book
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation because the behavioral level is not as highly abstracted as the system level nor is it as complex as the gate/transistor level. At the behavioral level there is a balanced degree of freedom to explore power reduction mechanisms, the power reduction opportunities are greater, and it can cost-effectively help in investigating lower power design alternatives prior to actual circuit layout or silicon implementation.The book is a self-contained low-power, high-level synthesis text for Nanoscale VLSI design engineers and researchers. Each chapter has simple relevant examples for a better grasp of the principles presented. Several algorithms are given to provide a better understanding of the underlying concepts. The initial chapters deal with the basics of high-level synthesis, power dissipation mechanisms, and power estimation. In subsequent parts of the text, a detailed discussion of methodologies for the reduction of different types of power is presented including:
• Power Reduction Fundamentals
• Energy or Average Power Reduction
• Peak Power Reduction
• Transient Power Reduction
• Leakage Power Reduction
Low-Power High-Level Synthesis for Nanoscale CMOS Circuits provides a valuable resource for the design of low-power CMOS circuits.
Bibliographic Information
Book Title: Low-Power High-Level Synthesis for Nanoscale CMOS Circuits
Authors: Priyardarsan Patra, Elias Kougianos, Nagarajan Ranganathan, Saraju P. Mohanty
DOI: https://doi.org/10.1007/978-0-387-76474-0
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2008
Hardcover ISBN: 978-0-387-76473-3Published: 07 July 2008
Softcover ISBN: 978-1-4419-4554-9Published: 05 November 2010
eBook ISBN: 978-0-387-76474-0Published: 31 May 2008
Edition Number: 1
Number of Pages: XXXII, 302
Number of Illustrations: 20 b/w illustrations
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Computer-Aided Engineering (CAD, CAE) and Design, Computer Hardware, Electrical Engineering