Writing Testbenches using SystemVerilog

1. Front Matter

   Pages i-xxv

   PDF

2. What is Verification?

   • Janick Bergeron

   Pages 1-22

3. Verification Technologies

   • Janick Bergeron

   Pages 23-76

4. The Verification Plan

   • Janick Bergeron

   Pages 77-111

5. High-Level Modeling

   • Janick Bergeron

   Pages 113-196

6. Stimulus and Response

   • Janick Bergeron

   Pages 197-278

7. Architecting Testbenches

   • Janick Bergeron

   Pages 279-331

8. Simulation Management

   • Janick Bergeron

   Pages 333-370

9. Back Matter

   Pages 371-411

   PDF

If you survey hardware design groups, you will learn that between 60% and 80% of their effort is dedicated to verification. This may seem unusually large, but I include in "verification" all debugging and correctness checking activities, not just writing and running testbenches. Every time a hardware designer pulls up a waveform viewer, he or she performs a verification task. With today’s ASIC and FPGA sizes and geometries, getting a design to fit and run at speed is no longer the main challenge. It is to get the right design, working as intended, at the right time. Unlike synthesizable coding, there is no particular coding style nor language required for verification. The freedom of using any l- guage that can be interfaced to a simulator and of using any features of that language has produced a wide array of techniques and approaches to verification. The continued absence of constraints and historical shortage of available expertise in verification, c- pled with an apparent under-appreciation of and under-investment in the verification function, has resulted in several different ad hoc approaches. The consequences of an informal, ill-equipped and understaffed verification process can range from a non-functional design requiring several re-spins, through a design with only a s- set of the intended functionality, to a delayed product shipment.

• Generator
• SystemVerilog
• Verilog
• model
• modeling
• simulation
• verification
• quality control, reliability, safety and risk

From the reviews:

"The book provides verification engineers with an introduction to all elements of a modern, scalable verification environment and a foundation for adopting the advanced verification methodology detailed in the Verification Methodology Manual for SystemVerilog … . ‘Mr. Bergeon has once again written a book that is a standard-bearer for engineers tasked with verifying RTL and systems design’ … . the strategies and methodologies put forth by Mr. Bergeron has become more important to the success of every verification project." (EE Times, April, 2006)

• Synopsys, Inc., USA

  Janick Bergeron

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