1. A monotonic SAR ADC with system-level error correction

   • Junfeng Gao
   • Guangjun Li
   • Qiang Li

   OriginalPaper 01 May 2015 Pages: 1 - 8

   

2. A low-power ADC with compact AGC loop for LR-WPAN receivers

   • Zuochen Shi
   • Yintang Yang
   • Di Li

   OriginalPaper 25 April 2015 Pages: 9 - 18

   

3. Reduction of 1/f ³ phase noise in LC oscillator with improved self-switched biasing

   • Nan Chen
   • Shengxi Diao
   • Fujiang Lin

   OriginalPaper 27 May 2015 Pages: 19 - 27

   

4. A 0.5–2.0 GHz injection locked oscillator cascade for parallel wideband RF spectrum sensing

   • Vishal Khatri
   • Gaurab Banerjee

   OriginalPaper 24 May 2015 Pages: 29 - 42

   

5. Analysis and design of wideband distributed VCOs based on switched-cells tuning technique

   • Francesco Cannone
   • Gianfranco Avitabile

   OriginalPaper Open access 13 May 2015 Pages: 43 - 51

   

6. Compact models and delay computation of sub-threshold interconnect circuits

   • Rohit Dhiman
   • Rohit Sharma
   • Rajeevan Chandel

   OriginalPaper 21 May 2015 Pages: 53 - 65

   

7. Modelling of direct tunneling gate leakage current of floating-gate CMOS transistor in sub 100 nm technologies

   • Zina Saheb
   • Ezz I. El-Masry

   OriginalPaper 17 May 2015 Pages: 67 - 73

   

8. A transconductance boosted CMOS current differencing transconductance amplifier (TBCDTA) and its application

   • Shireesh Kumar Rai
   • Maneesha Gupta

   Mixed Signal Letter 01 May 2015 Pages: 75 - 88

   

9. SAR ADC architecture with 98.8 % reduction in switching energy over conventional scheme

   • Yuhua Liang
   • Zhangming Zhu
   • Ruixue Ding

   Mixed Signal Letter 25 April 2015 Pages: 89 - 96

   

10. An active-RC reconfigurable lowpass-polyphase biquad filter for wireless receiver

    • C. Huang
    • C. Chen
    • J. H. Wu

    Mixed Signal Letter 03 May 2015 Pages: 97 - 105

    

11. Voltage differencing transconductance amplifier based resistorless and electronically tunable wave active filter

    • Neeta Pandey
    • Praveen Kumar
    • Sajal K. Paul

    Mixed Signal Letter 05 May 2015 Pages: 107 - 117

    

12. A 22 nm FinFET based 6T-SRAM cell design with scaled supply voltage for increased read access time

    • I. Manju
    • A. Senthil Kumar

    Mixed Signal Letter 28 April 2015 Pages: 119 - 126

    

13. “Skip–Swap” method instead of “Skip–Fill” method in background calibration of pipelined ADCs

    • Meysam Mohammadi Khanghah
    • Amir Alipour Asl
    • Khosrov Dabbagh Sadeghipour

    Mixed Signal Letter 08 May 2015 Pages: 127 - 135

    

14. A 40 MHz-BW 12-bit continuous-time ∆Σ modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS

    • Xinpeng Xing
    • Maarten De Bock
    • Georges Gielen

    Mixed Signal Letter 20 May 2015 Pages: 137 - 148