Abstract
We automatically generate assertions from Transaction Level Model (TLM) simulation traces. The generated assertions express design specifications in the form of linear temporal logic with quantitative temporal constraints [4]. We first generate the assertions without regard to the quantitative time constraints. They are mined in the form of frequent patterns in the simulation traces. We mine simulation traces using episode mining to identify frequent episodes comprising function calls and events. We then annotate the episodes with real time parameters to express quantitative time constraints among the function calls or events in the episode. When mining such TLM assertions, we employ symbolic execution to generalize the parameters and return values of function calls in the traces to help the mining engine generate high quality assertions. We have constructed a realistic AXI-based interconnection network platform that we demonstrate experimental results on. We show that our technique efficiently generates high quality performance and functional assertions on the AXI-based platform as well as a transaction level AMBA-based DMA controller. We demonstrate that episode mining is more scalable and able to generate a more compact set of high quality TLM assertions than previous efforts using sequential pattern mining. The number of generated assertions using episode mining can be reduced by up to 228 times, and the time interval between two events/function calls in each assertion is smaller than 50 time units.
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Notes
In this paper, we use A → B to represent the form of linear temporal logic: A ⇒ F B
Similarly, we use A → [a, b] B to represent the form of linear temporal logic with quantitative time constraint: A ⇒ F [a, b] B
References
AMBA-PV extensions to OSCI TLM 2.0 developer guide. http://infocenter.arm.com
AXI platform web page: http://code.google.com/p/tlmviolation
Ayres J, Flannick J, Gehrke J, Yiu T (2002) Sequential pattern mining using a bitmap representation. In: Proceedings of the eighth ACM SIGKDD international conference on knowledge discovery and data mining, pp 429–435
Bellini P, Mattolini R, Nesi P (2000) Temporal logics for real-time system specification. ACM Comput Surv 32(1):12–42
Bombieri N, Fummi F, Pravadelli G, Fedeli A (2007) Hybrid, incremental assertion-based verification for tlm design flows, design & test of computers. IEEE 24(2)140–152
Cai L, Gajski D (2003) Transaction level modeling: an overview. In: First IEEE/ACM/IFIP international conference on hardware/software codesign and system synthesis, pp 19–24
Chang P-H, Wang L-C (2010) Automatic assertion extraction via sequential data mining of simulation traces. In: Design automation conference (ASP-DAC), 2010 15th Asia and South Pacific, pp 607–612
Chen X, Hsieh H, Balarin F, Watanabe Y (2004) Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8):1243–1255
Cheng X, Hsiao MS (2008) Simulation-directed invariant mining for software verification. In: Proceedings of DATE, pp 682–687
Ecker W, Esen V, Steininger T, Velten M, Hull M (2006) Specification language for transaction level assertions. In: High-level design, validation, and test workshop, IEEE international, pp 77–84
Ernst MD, Cockrell J, Griswold WG, Notkin D (1999) Dynamically discovering likely program invariants to support program evolution. In: Proceedings of the 21st international conference on software engineering, pp 213–224
Han J, Kamber M (2006) Data mining: conceptes and techniques. Morgan Kaufmann Publishers, San Francisco, CA
Hangal S, Chandra N, Narayanan S, Chakravorty S (2005) Iodine: a tool to automatically infer dynamic invariants for hardware designs. In: Proceedings of DAC, pp 775–778
IEEE standard for system verilog: unified hardware design, specification, and verification language (2005) IEEE Std 1800–2005, pp 0–648
King JC (1976) Symbolic execution and program testing. Commun ACM 19(7)385–394
Kroening D, Sharygina N (2005) Formal verification of systemc by automatic hardware/software partitioning. In: Proceedings of the 2nd ACM/IEEE international conference on formal methods and models for co-design, pp 101–110
Li W, Forin A, Seshia SA (2010) Scalable specification mining for verification and diagnosis. In: Proceedings of the 47th design automation conference, pp 755–760
Liu L, Vasudevan S (2010) STAR: generating input vectors for design validation by static analysis of rtl. In: IEEE international high level design validation and test workshop
Liu L, Sheridan D, Athavale V, Vasudevan S (2011) Automatic generation of assertions from system level design using data mining. In: ACM/IEEE conference on formal methods and models for codesign
Lo D, Khoo S-C (2006) Smartic: towards building an accurate, robust and scalable specification miner. In: Proceedings of the 14th ACM SIGSOFT international symposium on Foundations of software engineering, pp 265–275
Mannila H, Toivonen H, Inkeri Verkamo A (1997) Discovery of frequent episodes in event sequences. Data Min Knowl Discov 1(3):259–289
Pei J, Han J, Mortazavi-asl B, Pinto H, Chen Q, Dayal U, chun Hsu M (2001) Prefixspan: mining sequential patterns efficiently by prefix-projected pattern growth. In: Proceedings of the 17th international conference on data engineering
Pierre L, Ferro L (2008) A tractable and fast method for monitoring systemc tlm specifications. IEEE Trans Comput 57(10):1346–1356
Pnueli A (1977) The temporal logic of programs. In: Proceedings of FOCS, pp 46–57
Srikant R, Agrawal R (1996) Mining sequential patterns: generalizations and performance improvements. In: Proceedings of the 5th international conference on extending database technology: advances in database technology, pp 3–17
SystemC web page: http://www.systemc.org
Tabakov D, Vardi MY, Kamhi G, Singerman E (2008) A temporal language for systemc. In: Proceedings of the 2008 international conference on formal methods in computer-aided design, pp 22:1–22:9
Vasudevan S, Sheridan D, Tcheng D, Patel S, Tuohy W, Johnson D (2010) Goldmine: automatic assertion generation using data mining and static analysis. In: Proceedings of DATE
Zaki MJ (2001) Spade: an efficient algorithm for mining frequent sequences. Mach Learn 42(1–2)31–60
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Liu, L., Vasudevan, S. Automatic Generation of System Level Assertions from Transaction Level Models. J Electron Test 29, 669–684 (2013). https://doi.org/10.1007/s10836-013-5403-y
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DOI: https://doi.org/10.1007/s10836-013-5403-y