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A low-complexity digital background calibration of sample-time error in time-interleaved A/D converters

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Abstract

A digital background calibration technique to estimate the sample-time error (timing-skew) in time-interleaved ADCs is presented. Compared to the state-of-the-art, this technique requires a simpler digital block and, hence, a lower power dissipation. The proposed technique detects timing skew for each channel by means of finding zero-crossing samples with respect to a reference comparator. Simulation results show that it can effectively correct timing errors for any type of input signal up to Nyquist, and achieves a high convergence speed with a very low computational complexity.

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Notes

  1. When a zero-crossing occurs between the sampling instants of the reference ADC and the ADC channel, it can randomly happen any time between them. Thus, Δt 1 and Δt 2 are considered as similar random variables.

  2. This update step size controls the speed of the ΔT convergence. However, its value is normally very small to reduce the effect of E[m] variance on the estimation of ΔT.

References

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Authors and Affiliations

  1. Ferdowsi University of Mashhad, Mashhad, Iran

    Amir Bazrafshan & Mohammad Taherzadeh-Sani

  2. Université du Québec à Montréal, Montreal, Canada

    Frederic Nabki

Authors
  1. Amir Bazrafshan
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  2. Mohammad Taherzadeh-Sani
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  3. Frederic Nabki
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Correspondence to Amir Bazrafshan.

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Bazrafshan, A., Taherzadeh-Sani, M. & Nabki, F. A low-complexity digital background calibration of sample-time error in time-interleaved A/D converters. Analog Integr Circ Sig Process 76, 245–249 (2013). https://doi.org/10.1007/s10470-013-0078-y

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  • DOI: https://doi.org/10.1007/s10470-013-0078-y

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