Abstract
Discrete Wavelet Transform (DWT) calculations form an inherent part of many signal processing applications. Application specific instructions provide a means to increase performance and efficiency of System-on-Chip (SoC) requiring DWT operations. In this paper, lifting scheme based hardware for efficient DWT calculation, is implemented as an instruction to enhance the performance of an SoC. The hardware is integrated using the coprocessor interface of the SPARCv8 ISA based LEON3 processor. This method for attaching lifting hardware is found to be much more efficient than the prevalent system-bus based integration. The performance measure is provided in terms of CPI and MIPS along with FPGA and ASIC implementation results of the SoC.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
O’Melia, S., Elbirt, A.J.: Enhancing the performance of symmetric-key cryptography via instruction set extensions. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18(11), 1505–1518 (2010)
Sun, F., Ravi, S., Jha, N.K.: A synthesis methodology for hybrid custom instruction and coprocessor generation for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circ. Syst. 26(11), 2035–2045 (2007)
Sweldens, W.: The lifting scheme: a custom-design construction of biorthogonal wavelets. Appl. Comput. Harmonic Anal. 3(2), 186–200 (1996)
Potdar, V.M., Han, S., Chang, E.: A survey of digital image watermarking techniques. In: IEEE International Conference on Industrial Informatics (2005)
Badawy, W., Weeks, M., Zhang, G., Talley, M., Bayoumi, M.A.: MRI data compression using a 3-D discrete wavelet transform. IEEE Eng. Med. Biol. Mag. 21(4), 95–103 (2002)
Shirazi, F.A., Mahjoob, M.J.: Application of discrete wavelet transform (DWT) in combustion failure detection of IC engines. In: International Symposium on Image and Signal Processing and Analysis ISPA (2007)
Mohanty, B.K., Mahajan, A., Meher, P.K.: Area- and power-efficient architecture for high-throughput implementation of lifting based 2-D DWT. IEEE Trans. Circ. Syst. II Express Briefs 59(7), 434–438 (2012)
Zhang, W., Jiang, Z., Gao, Z., Liu, Y.: An efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Circ. Syst. II Express Briefs 59(3), 158–162 (2012)
Hu, Y., Jong, C.C.: A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT. IEEE Trans. Signal Process. 61(20), 4975–4987 (2013)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Bansal, R., Jatav, M.K., Karmakar, A. (2017). A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_68
Download citation
DOI: https://doi.org/10.1007/978-981-10-7470-7_68
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7469-1
Online ISBN: 978-981-10-7470-7
eBook Packages: Computer ScienceComputer Science (R0)