Abstract
A multi-bit antifuse-type one-time programmable (OTP) memory is designed, which has a smaller area and a shorter programming time compared with the conventional single-bit antifuse-type OTP memory. While the conventional antifuse-type OTP memory can store a bit per cell, a proposed OTP memory can store two consecutive bits per cell through a data compression technique. The 1 kbit OTP memory designed with Magnachip 0.18 μm CMOS (complementary metal-oxide semiconductor) process is 34% smaller than the conventional single-bit antifuse-type OTP memory since the sizes of cell array and row decoder are reduced. And the programming time of the proposed OTP memory is nearly 50% smaller than that of the conventional counterpart since two consecutive bytes can be compressed and programmed into eight OTP cells at once. The layout area is 214 μm × 327 μm, and the read current is simulated to be 30.4 μA.
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Foundation item: Project supported by the 2nd Stage of Brain Korea; Project supported by the Korea Research Foundation
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Li, Lz., Lee, J.H., Kim, T.H. et al. Design of small-area multi-bit antifuse-type 1 kbit OTP memory. J. Cent. South Univ. Technol. 16, 467–473 (2009). https://doi.org/10.1007/s11771-009-0078-3
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DOI: https://doi.org/10.1007/s11771-009-0078-3