Skip to main content
Log in

Design and Evaluation of CNFET-Based Quaternary Circuits

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents novel high-performance and PVT tolerant quaternary logic circuits as well as efficient quaternary arithmetic circuits for nanoelectronics. These Carbon Nanotube FET (CNFET)-based circuits are compatible with the recent technologies and are designed based on the conventional CMOS architecture, while the previous quaternary designs used methods which are not suitable for nanoelectronics and have become obsolete. The proposed designs are robust and have large noise margins and high driving capability. The singular characteristics of CNFETs, such as the capability of having the desired threshold voltage by regulating the diameters of the nanotubes, make them very appropriate for voltage-mode multiple-threshold circuits design. The proposed circuits are examined, using Synopsys HSPICE with the standard 32 nm-CNFET technology in various situations and different supply voltages. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process, voltage and temperature variations.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14

Similar content being viewed by others

References

  1. G. Cho, Y.-B. Kim, F. Lombardi, M. Choi, Performance evaluation of CNFET-based logic gates, in Proc IEEE International Instrumentation and Measurement Technology Conference, 5–7 May (2009), pp. 909–912

    Google Scholar 

  2. R.C.G. Da Silva, H. Boudinov, L. Carro, A novel voltage-mode CMOS quaternary logic design. IEEE Trans. Electron Devices 53(6), 1480–1483 (2006)

    Article  Google Scholar 

  3. S.R.P.R. Datla, M.A. Thornton, Quaternary voltage-mode logic cells and fixed-point multiplication circuits, in Proc. IEEE International Symposium on Multiple-Valued Logic, 26–28 May (2010), pp. 128–133

    Chapter  Google Scholar 

  4. J. Deng, Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors. Doctoral Dissertation. Stanford University, 2007

  5. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron Devices 54(12), 3186–3194 (2007)

    Article  Google Scholar 

  6. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54(12), 3195–3205 (2007)

    Article  Google Scholar 

  7. E. Dubrova, Multiple-valued logic in VLSI: challenges and opportunities, in Proc 17th NORCHIP Conference, Nov. (1999), pp. 340–350

    Google Scholar 

  8. A. Hueng, H.T. Mouftah, Depletion/enhancement CMOS for a low power family of three-valued logic circuits. IEEE J. Solid-State Circuits 20(2), 609–616 (1985)

    Article  Google Scholar 

  9. S.L. Hurst, Multiple-valued logic—its status and its future. IEEE Trans. Comput. 33(12), 1160–1179 (1984)

    Article  Google Scholar 

  10. P. Keshavarzian, K. Navi, Universal ternary logic circuit design through carbon nanotube technology. Int. J. Nanotechnol. 6(10–11), 942–953 (2009)

    Article  Google Scholar 

  11. Y.-B. Kim, Challenges for nanoscale MOSFETs and emerging nanoelectronics. Trans. Electr. Electron. Mater. 11(3), 93–105 (2010)

    Article  Google Scholar 

  12. Y.B. Kim, Y.-B. Kim, F. Lombardi, Novel design methodology to optimize the speed and power of the CNTFET circuits, in Proc IEEE International Midwest Symposium on Circuits and Systems, 2–5 Aug. (2009), pp. 1130–1133

    Chapter  Google Scholar 

  13. Y. Li, W. Kim, Y. Zhang, M. Rolandi, D. Wang, Growth of single-walled carbon nanotubes from discrete catalytic nanoparticles of various sizes. J. Phys. Chem. B 105(46), 11424–11431 (2001)

    Article  Google Scholar 

  14. A. Lin, N. Patil, K. Ryu, A. Badmaev, L.G. De Arco, C. Zhou, S. Mitra, H.-S.P. Wong, Threshold voltage and on–off ratio tuning for multiple-tube carbon nanotube FETs. IEEE Trans. Nanotechnol. 8(1), 4–9 (2009)

    Article  Google Scholar 

  15. S. Lin, Y.-B. Kim, F. Lombardi, A novel CNFET based ternary logic gate design, in Proc IEEE International Midwest Symposium on Circuits and Systems, 2–5 Aug. (2009), pp. 435–438

    Chapter  Google Scholar 

  16. S. Lin, Y.-B. Kim, F. Lombardi, Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr. VLSI J. 43(2), 176–187 (2010)

    Article  Google Scholar 

  17. S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)

    Article  Google Scholar 

  18. P.L. McEuen, M. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(1), 78–85 (2002)

    Article  Google Scholar 

  19. M.H. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5(4), 285–296 (2011)

    Article  Google Scholar 

  20. M.H. Moaiyeri, R. Chavoshisani, A. Jalali, K. Navi, O. Hashemipour, High-performance mixed-mode universal min-max circuits for nanotechnology. Circuits Syst. Signal Process. 31(2), 465–488 (2012)

    Article  MathSciNet  Google Scholar 

  21. H.T. Mouftah, I.B. Jordan, Integrated circuits for ternary logic, in Proc. International Symposium on Multiple Valued Logic, May (1974), pp. 285–302

    Google Scholar 

  22. H.T. Mouftah, K.C. Smith, Injected voltage low-power CMOS for 3-valued logic. IEE Proc. G, Electron. Circuits Syst. 129(6), 270–272 (1982)

    Article  Google Scholar 

  23. K. Navi, M.H. Moaiyeri, R. Faghih Mirzaee, O. Hashemipour, B. Mazloom Nezhad, Two new low-power full adders based on majority-not gates. Microelectron. J. 40(1), 126–130 (2009)

    Article  Google Scholar 

  24. K. Navi, A. Doostaregan, M.H. Moaiyeri, O. Hashemipour, A hardware-friendly arithmetic method and efficient implementations for designing digital fuzzy adders. Fuzzy Sets Syst. 185(1), 111–124 (2011)

    Article  MathSciNet  MATH  Google Scholar 

  25. Y. Ohno, S. Kishimoto, T. Mizutani, T. Okazaki, H. Shinohara, Chirality assignment of individual single-walled carbon nanotubes in carbon nanotube field-effect transistors by micro-photocurrent spectroscopy. Appl. Phys. Lett. 84(8), 1368–1370 (2004)

    Article  Google Scholar 

  26. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson, H.-S.P. Wong, S. Mitra, Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes. IEEE Trans. Nanotechnol. 10(4), 744–750 (2011)

    Article  Google Scholar 

  27. A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005)

    Article  Google Scholar 

  28. A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. 54(11), 2391–2401 (2007)

    Article  Google Scholar 

  29. H. Shahidipour, A. Ahmadi, K. Maharatna, Effect of variability in SWCNT-based logic gates, in Proc International Symposium on Integrated Circuits, 14–16 Dec. (2009), pp. 252–255

    Google Scholar 

  30. A. Srivastava, Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits. Microelectron. Reliab. 40(12), 2107–2110 (2000)

    Article  Google Scholar 

  31. A. Srivastava, K. Venkatapathy, Design and implementation of a low power ternary full adder. VLSI Des. 4(1), 75–78 (1996)

    Article  Google Scholar 

  32. M.A. Tehrani, F. Safaei, M.H. Moaiyeri, K. Navi, Design and implementation of multi-stage interconnection networks using quantum-dot cellular automata. Microelectron. J. 42(6), 913–922 (2011)

    Article  Google Scholar 

  33. I. Thoidis, D. Soudris, I. Karafyllidis, S. Christoforidis, A. Thanailakis, Quaternary voltage-mode CMOS circuits for multiple-valued logic. IEE Proc., Circuits Devices Syst. 145(2), 71–77 (1998)

    Article  Google Scholar 

  34. P.K.S. Vasundara, K.S. Gurumurthy, Quaternary CMOS combinational logic circuits, in Proc. IEEE International Conference on Information and Multimedia Technology, 16–18 Dec. (2009), pp. 538–542

    Google Scholar 

  35. B. Wang, P. Poa, L. Wei, L. Li, Y. Yang, Y. Chen, (n,m) selectivity of single-walled carbon nanotubes by different carbon precursors on Co-Mo catalysts. J. Am. Chem. Soc. 129(9), 9014–9019 (2007)

    Article  Google Scholar 

  36. Y. Yasuda, Y. Tokuda, S. Zaima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. Solid-State Circuits SC-21(1), 162–168 (1986)

    Article  Google Scholar 

  37. J. Zhang, N. Patil, A. Lin, H.-S.P. Wong, S. Mitra, Carbon nanotube circuits: living with imperfections and variations, in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), 8–12 Mar. (2010), pp. 1159–1164

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Keivan Navi.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Moaiyeri, M.H., Navi, K. & Hashemipour, O. Design and Evaluation of CNFET-Based Quaternary Circuits. Circuits Syst Signal Process 31, 1631–1652 (2012). https://doi.org/10.1007/s00034-012-9413-2

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-012-9413-2

Keywords

Navigation