Abstract
Addition is a primitive operation for most arithmetic functions, so that FPGA vendors have dedicated a particular attention to the design of optimized adders. As a consequence, in many cases the synthesis tools are able to generate fast and cost-effective adders from simple VHDL expressions. Only in the case of relatively long operands can it be worthwhile to consider more complex structures such as carry-skip, carry-select and logarithmic adders.
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Parhami B (2000) Computer arithmetic: algorithms and hardware design. Oxford University Press, New York
Ling H (1981) High-speed binary adder. IBM J Res Dev 25(3):156–166
Brent R, Kung HT (1982) A regular layout for parallel adders. IEEE Trans Comput C-31:260–264
Ladner RE, Fischer MJ (1980) Parallel prefix computation. J ACM 27:831–838
Ercegovac MD, Lang T (2004) Digital arithmetic. Morgan Kaufmann, San Francisco
Deschamps JP, Bioul G, Sutter G (2006) Synthesis of arithmetic circuits. Wiley, New York
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© 2012 Springer Science+Business Media Dordrecht
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Deschamps, JP., Sutter, G.D., Cant, E. (2012). Adders. In: Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering, vol 149. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2987-2_7
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DOI: https://doi.org/10.1007/978-94-007-2987-2_7
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