Abstract
FIR filter plays a very important role in the digital image and digital signal processing. This paper describes a design and optimization of demoboard based on Xilinx’s spartan6 chip FIR filter. First, it needs to select the appropriate FIR filter structure for reducing the waste of FPGA logic resources; then, the FIR filter with multipliers and adders need to be improved and optimized, and FIR filter model is built by using of Simulink of Matlab. Finally, we need to convert FIR model into project file by System Generator, and use the software ISE to edit, synthesize, map and layout for project file. After then, configuration file is generated, and it is downloaded into the FPGA for realizing optimization of FIR filter and hardware design.
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Wang, J., Wang, L., Yuan, Z. (2013). Study and Optimization of FIR Filters Based on FPGA. In: Lu, W., Cai, G., Liu, W., Xing, W. (eds) Proceedings of the 2012 International Conference on Information Technology and Software Engineering. Lecture Notes in Electrical Engineering, vol 210. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34528-9_9
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DOI: https://doi.org/10.1007/978-3-642-34528-9_9
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