Abstract
This chapter reviews designs and prototypes of reconfigurable hardware implemented on a Field Programmable Gate Array (FPGA) to speedup ubiquitous linear algebra subroutines used in system security analysis. The grid operators use Energy Management System (EMS) software to analyze system security to assure normal operating state. EMS consists of three main computations: 1) state estimation, 2) contingency analysis, and 3) optimal power flow. These computations involve sparse linear algebra algorithms such as matrix orthogonal (QR) decomposition, Lower-Upper (LU) decomposition and matrix multiplication. Currently, EMS computations are performed on a general-purpose processor system. A benchmark study of several state-of-the-art sparse linear solver packages running on these systems reveals inefficient utilization of the floating-point computational throughput. A custom hardware sparse linear solver that maximizes floating-point hardware utilization based on pipeline architecture and efficient data caching offers an alternative. A prototype on reconfigurable hardware demonstrated that despite more than an order of magnitude deficit in clock speed as compared to general purpose processor based systems, a specialized sparse LU hardware running on FPGA is capable of an order of magnitude speedup relative to these systems for power system Jacobian matrix sparse LU decomposition. Performance analysis of sparse QR decomposition hardware showed a similar potential speedup over general-purpose processors.
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Nagvajara, P., Nwankpa, C., Johnson, J. (2013). Reconfigurable Hardware Accelerators for Power Transmission System Computation. In: Khaitan, S., Gupta, A. (eds) High Performance Computing in Power and Energy Systems. Power Systems. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32683-7_7
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DOI: https://doi.org/10.1007/978-3-642-32683-7_7
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