Abstract
In this paper, a novel method for multiple fault diagnosis is proposed using Genetic Algorithms. Fault diagnosis plays a major role in VLSI Design and Testing. The input test vectors required for testing should be compact and optimized .Genetic Algorithm is a search technique to find approximate solutions to optimization and search problems. The proposed technique uses binary strings as a substitute for chromosomes. The chromosomes (test vectors) are initialized randomly and their fitness value is evaluated. Genetic operations selection, crossover and mutation are performed on this initialized set (initial population) to reproduce better test vectors. The test vectors thus generated are reordered by using a reordering algorithm. The total switching activity among the reordered test vectors is thus optimized and hence the reduction of test power.
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References
Bushnell, M.L., Agarwal, V.D.: Essentials of Electronic Testing for Digital Memory and Mixed Signal VLSI Circuits. Kluwer Academic Publishers, London (2001)
Abramovici, M., Breuer, M.A., Friedman, A.D.: Digital Systems Testing and Testable Design. IEEE Press, New York (1990)
Lin, Y.-C., Cheng, K.T.: Multiple-Fault Diagnosis Based on Single fault activation and single output observation. In: Proceedings of Design, Automation and Test (2006)
Takahashi, H., Boateng, K.O., Saluja, K.K., Takamatsu, Y.: On diagnosing multiple stuck at faults using multiple and single fault simulation in combinational circuits. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 21(3), 362–368 (2002)
Wang, Z., Tsai, K.H., Marek-Sadowska, M., Rajski, J.: Multiple fault diagnosis using n-detection tests. In: Proceedings of 21st International Conference on Computer Design (2003)
Wang, Z., Tsai, K.H., Marek-Sadowska, M., Rajski, J.: An efficient and effective methodology on the multiple fault diagnosis. In: International Test Conference, Charlotte, NC, pp. 329–338 (2003)
Pan, Z., Chen, L., Liu, S., Zhang, G.: Neural Network approach for multiple fault test of digital circuits. In: International Conference on Intelligent Systems (2006)
Pan, Z., Chen, L., Zhang, G.: A New Method for the Detections of Multiple Faults Using Binary Decision Diagrams. Wuhan University Journal of Natural Sciences 11(6), 1943–1946 (2006)
Wang, Z., Marek-Sadowska, M., Tsai, K.-H., Rajski, J.: Analysis and methodology for Multiple Fault Diagnosis. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 25(3) (2006)
Takahashi, N., Ishiura, N., Yajima, S.: Fault Simulation for multiple faults by Boolean Function Manipulation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 13(4), 531–535 (1994)
Verreault, A., Aboulhamid, E.M., Karkouri, Y.: Multiple fault analysis using a fault dropping technique. In: Proceedings of 21st Fault Tolerant Computing Symposium (1991)
Lin, Y.-C., Lu, F., Cheng, K.T.: Multiple-Fault Diagnosis Based on Adaptive Diagnostic Test Pattern Generation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 26(5) (2007)
Huang, S.Y.: On improving the accuracy of multiple defect diagnosis. In: Proceedings of 19th IEEE VLSI Test Symposium, pp. 34–39 (2001)
O’Dare, M.J., Arslan, T.: Generating test patterns for VLSI circuits using a genetic Algorithm. IEEE Electronic Letters 30(10), 778–779 (1994)
Rudnick, E.M., Patel, J.H., Greenstein, G.S., Niermann, T.M.: A Genetic Algorithm Framework for Test Generation. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 16(9) (1997)
Papa, G., Garbolino, T., Novak, F., Lawiczka, A.H.: Deterministic Test Pattern Generator Design With Genetic Algorithm Approach. Journal of Electrical Engineering 58(3), 121–127 (2007)
Jha, N., Gupta, S.: Testing of Digital Systems.Cambridge University Press (2003)
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Anita, J.P., Vanathi, P.T. (2012). Multiple Fault Diagnosis and Test Power Reduction Using Genetic Algorithms. In: Mathew, J., Patra, P., Pradhan, D.K., Kuttyamma, A.J. (eds) Eco-friendly Computing and Communication Systems. ICECCS 2012. Communications in Computer and Information Science, vol 305. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32112-2_11
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DOI: https://doi.org/10.1007/978-3-642-32112-2_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32111-5
Online ISBN: 978-3-642-32112-2
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