Abstract
Coarse-Grained Reconfigurable Arrays (CGRAs) are a very promising platform, providing both, up to 10-100 MOps/mW of power efficiency and are software programmable. However, this cardinal promise of CGRAs critically hinges on the effectiveness of application mapping onto CGRA platforms. While previous solutions have greatly improved the computation speed, they have largely ignored the impact of the local memory architecture on the achievable power and performance. This paper motivates the need for memory-aware application mapping for CGRAs, and proposes an effective solution for application mapping that considers the effects of various memory architecture parameters including the number of banks, local memory size, and the communication bandwidth between the local memory and the external main memory. Our proposed solution achieves 62% reduction in the energy-delay product, which factors into about 47% and 28% reduction in the energy consumption and runtime, respectively, as compared to memory-unaware mapping for realistic local memory architectures. We also show that our scheme scales across a range of applications, and memory parameters.
This work was supported by the Korea Science and Engineering Foundation(KOSEF) NRL Program grant funded by the Korea government(MEST) (No. 2009-0083190), the Engineering Research Center of Excellence Program of Korea Ministry of Education, Science and Technology(MEST)/ Korea Science and Engineering Foundation(KOSEF) (R11-2008-007-01001-0), Seoul R&BD Program(10560), the Korea Research Foundation Grant funded by the Korean Government(MOEHRD) (KRF-2007-357-D00225), 2009 Research Fund of the UNIST (Ulsan National Institute of Science and Technology), and grants from Raytheon, Stardust foundation, and NSF (grant no. 0916652).
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Bormans, J.: Reconfigurable array processor satisfies multi-core platforms. Chip Design Magazine (2006)
Singh, H., Lee, M.-H., Lu, G., Bagherzadeh, N., Kurdahi, F., Filho, E.: Morphosys: An integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. 49(5), 465–481 (2000)
Kim, Y., Kiemb, M., Park, C., Jung, J., Choi, K.: Resource sharing and pipelining in coarse-grained reconfigurable architecture for domain-specific optimization. In: DATE 2005, Washington, DC, USA, pp. 12–17. IEEE Computer Society, Los Alamitos (2005)
Mei, B., Vernalde, S., Verkest, D., Lauwereins, R.: Design methodology for a tightly coupled vliw/reconfigurable matrix architecture: A case study. In: DATE 2004, p. 21224 (2004)
Hartenstein, R.: A decade of reconfigurable computing: a visionary retrospective. In: DATE 2001, Piscataway, NJ, USA, pp. 642–649. IEEE Press, Los Alamitos (2001)
Lee, J., Choi, K., Dutt, N.: Compilation approach for coarse-grained reconfigurable architectures. IEEE D&T 20, 26–33 (2003)
Lee, J., Choi, K., Dutt, N.: An algorithm for mapping loops onto coarse-grained reconfigurable architectures. ACM SIGPLAN Notices 38(7), 183–188 (2003)
Mei, B., Vernalde, S., Verkest, D., De Man, H., Lauwereins, R.: Dresc: a retargetable compiler for coarse-grained reconfigurable architectures, December 2002, pp. 166–173 (2002)
Park, H., Fan, K., Kudlur, M., Mahlke, S.: Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures. In: CASES 2006, pp. 136–146. ACM, New York (2006)
Hatanaka, A., Bagherzadeh, N.: A modulo scheduling algorithm for a coarse-grain reconfigurable array template. In: IPDPS 2007, March 2007, pp. 1–8 (2007)
Ahn, M., Yoon, J., Paek, Y., Kim, Y., Kiemb, M., Choi, K.: A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. In: DATE 2006, 3001 Leuven, Belgium, pp. 363–368. European Design and Automation Association (2006)
Yoon, J., Shrivastava, A., Park, S., Ahn, M., Jeyapaul, R., Paek, Y.: Spkm: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. In: ASP-DAC 2008, pp. 776–782 (2008)
Park, H., Fan, K., Mahlke, S., Oh, T., Kim, H., Kim, H.: Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: PACT 2008, pp. 166–176. ACM, New York (2008)
Venkataramani, G., Najjar, W., Kurdahi, F., Bagherzadeh, N., Bohm, W.: A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. In: CASES 2001, pp. 116–125. ACM Press, New York (2001)
Lee, W., Barua, R., Frank, M., Srikrishna, D., Babb, J., Sarkar, V., Amarasinghe, S.: Space-time scheduling of instruction-level parallelism on a raw machine. In: ASPLOS-VIII, pp. 46–57 (1998)
Bougard, B., De Sutter, B., Verkest, D., Van der Perre, L., Lauwereins, R.: A coarse-grained array accelerator for software-defined radio baseband processing. IEEE Micro 28(4), 41–50 (2008)
Thoziyoor, S., Muralimanohar, N., Ahn, J., Jouppi, N.: Cacti 5.1. Technical report (2008)
Dimitroulakos, G., Galanis, M., Goutis, C.: Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays. In: ASAP 2005, Washington, DC, USA, pp. 161–168. IEEE Computer Society, Los Alamitos (2005)
Lee, J., Choi, K., Dutt, N.: Evaluating memory architectures for media applications on coarse-grained reconfigurable architectures. In: Proc. ASAP, pp. 172–182. IEEE, Los Alamitos (2003)
Dimitroulakos, G., Georgiopoulos, S., Galanis, M., Goutis, C.: Resource aware mapping on coarse grained reconfigurable arrays. Microprocess. Microsyst. 33(2), 91–105 (2009)
Guthaus, M., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench: A free, commercially representative embedded benchmark suite. In: IWWC, pp. 3–14 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kim, Y., Lee, J., Shrivastava, A., Yoon, J., Paek, Y. (2010). Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays. In: Patt, Y.N., Foglia, P., Duesterwald, E., Faraboschi, P., Martorell, X. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2010. Lecture Notes in Computer Science, vol 5952. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11515-8_14
Download citation
DOI: https://doi.org/10.1007/978-3-642-11515-8_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11514-1
Online ISBN: 978-3-642-11515-8
eBook Packages: Computer ScienceComputer Science (R0)