Abstract
3D stacked chips have become a promising integration technology for modern systems. The complexity reached in multi-processor systems has increased the communication delays between processing cores, and an effective way to diminish this impact on communication is the 3D integration technology and the use of through-silicon vias (TSVs) for inter-layer communication. However, 3D chips present important thermal issues due to the presence of processing units with a high power density, which are not homogeneously distributed in the stack. Also, the presence of hot-spots creates thermal gradients that impact negatively on the system reliability and relate with the leakage power consumption. Thus, new approaches for thermal control of 3D chips are in great need. This paper discusses the use of a grid and non-uniform placement of TSVs as an effective mechanism for thermal balancing and control in 3D chips. We have modelled the material layers and TSVs mathematically using a detailed calibration phase based on a real 5-tier 3D chip stack, where several heaters and sensors are manufactured to study the heat diffusion. The obtained results show interesting conclusions and new in- sights in the area of thermal modeling and optimization for 3D chips using TSVs.
This work is partially funded by the Spanish Ministry under contract TIN2008-508.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Ayala, J.L., Sridhar, A., Pangracious, V., Atienza, D., Leblebici, Y. (2009). Through Silicon Via-Based Grid for Thermal Control in 3D Chips. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_14
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DOI: https://doi.org/10.1007/978-3-642-04850-0_14
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