Skip to main content

CMOS ADCs for Optical Communications

  • Chapter
  • First Online:

Abstract

This paper provides a systematic view of ADCs embedded in DSP receivers of coherent optical communications systems. The functionality, performance and CMOS implementation trade-offs are discussed with the focus on techniques achieving high sampling rate and bandwidth. High conversion rate is efficiently addressed by massive interleaving of lower speed SAR ADCs, while the bandwidth limitation is dealt with on both architectural and circuit design levels. In conclusion, results of a 40 Gs/s 6b-ADC implemented in 65 nm CMOS are demonstrated.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. Roberts K, Beckett D, Boertjes D, Berthold J, Laperle C (2010) 100 G and beyond with digital coherent signal processing. IEEE Commun Mag 48(7):62–69

    Article  Google Scholar 

  2. Ben-Hamida N, Greshishchev Y, Beggs B (2010) Advances in transceiver circuits to suit new optical modulation formats – a historical perspective. In: Forum F3-Transciever circuits for optical communications, Digest of technical papers international solid- state conference (ISSCC). IEEE, pp 514–515, Feb 2010 San-Francisco, USA

    Google Scholar 

  3. Schvan P, Bach J, Falt C, Flemke P, Gibbins R, Greshishchev Y, Ben-Hamida N, Pollex D, Sitch J, Wang S-C, Wolczanski J (2008) A 24 GS/s 6b ADC in 90 nm CMOS. In: International solid-state conference, Digest technical papers, pp 544–545, Feb 2008 San-Francisco, USA

    Google Scholar 

  4. Greshishchev YM, Aguirre J, Besson M, Gibbins R, Falt C, Flemke P, Ben-Hamida N, Pollex D, Schvan P, Wang S-C (2010) A 40 GS/s 6b ADC in 65 nm CMOS. In: International solid-state conference, Digest technical papers, pp 390–391, Feb 2010 San-Francisco, USA

    Google Scholar 

  5. Bower P, Dedic I (2011) High speed converters and DSP for 100 G and beyond. Opt Fiber Technol 17(5):464–471

    Article  Google Scholar 

  6. Schvan P, Pollex D, Wang S-C, Falt C, Ben-Hamida N (2006) A 22 GS/s 5b ADC in 0.13 um SiGe BiCMOS. In: International solid-state conference, Digest technical papers, pp 572–573, Feb 2006 San-Francisco, USA

    Google Scholar 

  7. Van de Plassche R (2003) CMOS integrated analog-to-digital and digital-to-analog converters. Kluwer, Boston

    MATH  Google Scholar 

  8. Cattermole KW (1973) Principles of pulse-code modulation. Iliffe Books, London

    Google Scholar 

  9. Shinagawa M, Akazawa Y, Wakimoto T (1990) Jitter analysis of high-speed sampling systems. IEEE J Solid-St Circ 25(1):220–224

    Article  Google Scholar 

  10. Poulton K, Neff R, Setterberg B, Wuppermann B, Kopley T, Jewett R, Pernillo J, Tan C, Montijo A (2003) A 20 GS/s 8b ADC with a 1 MB Memory in 0.18um CMOS. In: International solid-state conference, Digest technical papers, pp 318–319, Feb 2003 San-Francisco, USA

    Google Scholar 

  11. Black WC, Hodges DA (1980) Time interleaved converter array. In: International solid-state conference, Digest technical papers, pp 14–15, Feb 1980 San-Francisco, USA

    Google Scholar 

  12. Draxelmayr D (2004) A 6b 600 MHz 10 mW ADC array in digital 90 nm CMOS. In: International solid-state conference, Digest technical papers, pp 264–265, Feb 2004 San-Francisco, USA

    Google Scholar 

  13. Agnes A, Bonizzoni E, Malcovati P, Maloberti F (2008) A9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time–domain comparator. In: International solid-state conference, Digest technical papers, pp 246–247, Feb 2008 San-Francisco, USA

    Google Scholar 

  14. Alpman E, Lakdawal H, Carley LR, Soumyanath K (2009) A 1.1 V 50 mW 2.5 GS/s 7b time interleaved C-2C SAR ADC in 45 nm LP digital CMOS. In: International solid-state conference, Digest technical papers, pp 76–78, Feb 2009 San-Francisco, USA

    Google Scholar 

  15. Verbruggen B, Craninckx J, Kuijk M, Wambacq P, Van der Plas G (2010) A 2.6 mW 6b 2.2 GS/s 4-times interleaved fully dynamic pipelined ADC in 40 nm digital CMOS. In: International solid-state conference, Digest technical papers, pp 296–297, Feb 2010 San-Francisco, USA

    Google Scholar 

  16. Ahmed I, Mulder J, Johns DA (2009) A 50MS/s 9.9 mW pipelined ADC with 58 dB SNDR in 0.18 μm CMOS using capacitive charge-pumps. In: International solid-state conference, Digest technical papers, pp 164–165, Feb 2009 San-Francisco, USA

    Google Scholar 

  17. Crivelli D, Hueda M, Carrer H, Zachan J, Gutnik V, Del Barco M, Lopez R, Hatcher G, Finochietto J, Yeo M, Chartrand A, Swenson N, Voois P, Agazzi O (2012) A 40 nm CMOS single-chip 50 Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels. In: International solid-state conference, Digest technical papers, pp 328–329, Feb 2012 San-Francisco, USA

    Google Scholar 

  18. LeCroy product datasheet (2012) LabMasters 10 Zi high bandwidth oscilloscopes, LeCroy San-Francisco, USA

    Google Scholar 

  19. Pupalaikis PJ (2007) An 18 GHz bandwidth, 60 GS/s sample rate real-time waveform digitizing system. In: Microwave symposium, IEEE/MTT-S international, pp 195–198, June 2007 Honolulu, USA

    Google Scholar 

Download references

Acknowledgement

The author is grateful to colleagues P. Schvan, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, S.-C. Wang, and J. Wolczanski for contribution to the ADC design and characterization. Special thanks to K. Roberts, B. Beggs, and J. Sitch for system insight and support.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yuriy M. Greshishchev .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer Science+Business Media New York

About this chapter

Cite this chapter

Greshishchev, Y.M. (2013). CMOS ADCs for Optical Communications. In: van Roermund, A., Baschirotto, A., Steyaert, M. (eds) Nyquist AD Converters, Sensor Interfaces, and Robustness. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-4587-6_6

Download citation

  • DOI: https://doi.org/10.1007/978-1-4614-4587-6_6

  • Published:

  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-1-4614-4586-9

  • Online ISBN: 978-1-4614-4587-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics