Abstract
Dependent on where the errors are generated and how they affect the performance, errors in a current-steering DAC (CS-DAC) can be distinguished as non-mismatch errors (global errors) and mismatch errors (local errors). As mentioned in Sect. 2.4.3, regardless of whether the CS-DAC has a binary or thermometer or segmented architecture, it is composed of many current cells. If those current cells deviate from their ideal behavior differently, mismatch errors (such as amplitude and timing errors) are generated. If current cells perfectly match, i.e. no mismatch errors, non-mismatch errors, such as clock jitter, absolute duty-cycle error, finite output impedance and switching interferences, may still limit the DAC performance.
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Tang, Y., Hegt, H., van Roermund, A. (2013). Modeling and Analysis of Performance Limitations in CS-DACs. In: Dynamic-Mismatch Mapping for Digitally-Assisted DACs. Analog Circuits and Signal Processing, vol 92. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1250-2_3
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DOI: https://doi.org/10.1007/978-1-4614-1250-2_3
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