6.1 Introduction

In SRAM, random dopant fluctuations and critical dimension variations are not the only challenges that affect the reliability. Over the life time of a system, transistor I-V characteristics can be affected by phenomena such as Negative Bias Temperature Instability (NBTI), hot carrier effects, or time dependent dielectric breakdown. These changes to I-V characteristics from such phenomena affect the SRAM metrics and reliability. The NBTI is particularly a challenging problem because it not only changes the strength (reduction in trans-conductance and drain current) of PMOS transistor, but it does so over the life time of a system. It makes difficult to screen out SRAM bitcells that function immediately after processing but which will eventually fail due to NBTI. In nano-regime, this systematic reduction in PMOS transistor strength, due to NBTI over the life time severely degrades the SRAM metrics and poses a significant reliability concern as well as a limiting factor in future device scaling [48, 60].

In particular, for sub-threshold operating devices that demand for higher drive current, NBTI significantly enhances the threshold voltage and thereby reduction in drive current simultaneously [93]. The NBTI-induced shift in threshold voltage degrades the performance of CMOS digital circuits. However, degradation in performance can be off-set by up-sizing of the PMOS devices during the design phase. Subsequently, this leads to an increase in power and silicon area overhead. The area, power and performance trade-offs due to NBTI effect have been widely studied in [50, 62, 74, 87, 115]. In SRAM bitcells, these trade-offs do not work effectively, because up-sizing of the devices increase the power budget and reduces the cache density. Furthermore, stability of the SRAM bitcell is becoming a more sensitive issue and drastically shifts the Static Noise Margin (SNM) and Write Noise Margin (WNM) over the time due to aging effects.

The impact of NBTI on SRAM bitcell reliability and stability is a subject of recent interest. In [90], authors showed that NBTI could affect read SNM by as much as 8% at V DD  = 0. 8 V, and the effect is more dominant at lower V DD . Authors in [65], extended this study and show that the variation in read stability increases as well, leading to larger failure counts in an SRAM array. These results demonstrate that NBTI has a significant impact on bitcell reliability. However, several researchers have reported a relatively low impact of NBTI on shift in threshold voltage of PMOS [17, 71, 82] at higher V DD . Although such low sensitivities seem to contradict with results reported in [9, 64, 65, 90]. An important observation is that the low sensitivities were reported at relatively higher V DD ( ≥ 0.9), and may have underestimated the NBTI impact at lower voltages.

SRAM bitcells are also particularly more susceptible to the NBTI effect because of their topologies. Since, one of the PMOS transistors is always negative biased if the bitcell contents are not flipped, it introduces asymmetry in the standard 6T SRAM bitcell due to a shift in threshold voltage in either of PMOS devices. In asymmetric SRAM bitcell, one of the Voltage Transfer Curves (VTCs) moves horizontally, as a result one of the butterfly curve lobe becomes smaller than the other which makes the read SNM poor, and more susceptible to process variation and NBTI induced failures.

The effect of NBTI independently and along with process variations on standard 6T (symmetric and asymmetric) SRAM bitcells and read static noise margin free 6T SRAM bitcell based cache configurations, are investigated in this chapter. In standard 6T SRAM bitcell, symmetric and asymmetric (dual-V TH ) SRAM bitcell based caches are considered. Symmetric 6T SRAM bitcells are generally used for implementation of high performance and high density caches. While, asymmetric SRAM bitcell based caches, designed with dual-V TH technology have been recently studied for their strong potential of leakage power savings [8, 81]. In asymmetric SRAM bitcells, sub-threshold leakage current devices are made of high V TH , while assuming the skewed distribution of storage bit ‘0’. The read static noise margin free SRAM bitcells consist of an isolated read-port and a cross-coupled inverter pair have recently attracted a lot of attention [25, 98, 108]. In these bitcells data storage nodes are isolated by providing a separate read-port (read current path), hence, there is no degradation in read SNM during the read cycle, referred as read SNM free SRAM bitcells.

It is investigated that employing different power saving strategies to the caches can recover a substantial portion of the stability noise margins (SNM and WNM) lost due to the predominant occurrence of logic ‘0’ being stored in caches. Based on different power saving strategies proposed in [69], six different cache configurations are formed and their duty cycles are derived from the average inactive time experienced by the cache blocks for different applications. This leads to an additional design consideration while determining which of the power saving strategies should be applied in cache design, particularly if lifetime operation is a prime concern. Furthermore, study of the intra-die process variations employing different SRAM bitcells based caches for different cache configuration is also done along with the NBTI.

6.2 The Physics of Negative Bias Temperature Instability (NBTI) and Its Impact

The NBTI effect becomes a practical concern in nano-regime CMOS technologies due to exponential dependence on oxide thickness and temperature [27]. NBTI causes an absolute increase in PMOS devices threshold voltage which contributes to degradation of the mobility, transconductance and drain current. Although NMOS devices can be damaged due to NBTI stress, however, the damage is not activated in the operational configuration of the NMOS device, and hence, PMOS devices typically receive high emphasis. The NBTI phenomenon that causes the absolute increase in threshold voltage (V TH ) of a PMOS transistor due to the formation of interface traps with respect to time. Under the negative bias condition (i.e. \({V }_{GS} = -{V }_{DD}\)) of a PMOS transistor, interface states and traps are generated as the hydrogen diffuses toward the gate. This phase of NBTI is called stress, as shown in Fig. 6.1a. The NBTI causes interface states and traps fixed positive charge in the oxide, the question naturally arises: “How do these interface states and fixed charges affect the device operation?”

Fig. 6.1
figure 1

PMOS biasing transistor in the stress and recovery phases due to NBTI

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From the physics of MOSFET device, the threshold voltage of a device is proportional to the number of charges over the capacitance of the gate oxide. The charges in a device can be fixed positive and that have populated an interface state. Changing the fixed charges and interface states within the device will result in a V TH shift. As a result, other device parameters such as the drain current and transconductance are subsequently affected. Drain current degradation due to V TH shifts impact matched devices and analog circuits greatly. It also degrade device performance in a circuit, as a result, leading to timing issues and circuit failure.

In Fig. 6.1b, when voltage of the gate is set to V DD then no new interface traps are generated while hydrogen diffuses back and anneals the broken bonds. However, full recovery of the traps becomes impossible since hydrogen is no longer available and this is referred as a recovery phase. Thanks to annealing process for dynamically recovering the threshold voltage during the recovery phase and thereby a significant amount of performance and circuit stability can be recovered. A circuit designed for skewed activity, while keeping the dynamic recovery of threshold voltage in mind can greatly reduce the ageing effect due to NBTI. Specifically for SRAM bitcells where one of the PMOS transistors is always in stress mode.

It is believed that the NBTI phenomenon involves a Reaction–Diffusion (R-D) process, and that the stress and recovery phases are successfully analyzed using the R-D model available on the PTM website [88, 124], and explained in more details in [3, 107], as follows:

$$\begin{array}{rcl} \Delta \vert {V }_{TH}\vert & =& \sqrt{{K}_{v }^{2 }{(t - {t}_{0 } )}^{0.5 } + \Delta {V }_{TH0 }^{2}} + {\delta }_{v}\ \ (stress) \\ & =& (\Delta {V }_{TH0} + {\delta }_{v})\left [1 -\sqrt{\eta (t - {t}_{0 } )/t}\right ]\ \ (recovery) \\ \end{array}$$

where

$$\begin{array}{rcl}{ K}_{v}& =& A{T}_{ox}\sqrt{{C}_{ox } ({V }_{GS } - {V }_{TH } )}.exp\left (\frac{{E}_{ox}} {{E}_{o}} \right ). \\ & & \left [1 - \frac{{V }_{DS}} {\alpha ({V }_{GS} - {V }_{TH})}\right ].\left (-\frac{{E}_{ox}} {{E}_{o}} \right ) \\ \end{array}$$

and

$${E}_{ox} = ({V }_{GS} - {V }_{TH})/{T}_{ox}$$
(6.1)

where, change of V TH0 (ΔV TH0) is due to stress or recovery happens at t = t0, the process and design parameters are V DS , V GS , V TH , T and T OX are scalable with model. The constants η, α, E0, δ v and E a are extracted from the technology parameters.

According to Eqs. 6.1, there are a number of factors that influence the shift in threshold voltage due to NBTI. There is a positive relationship among these parameters such as temperature, supply voltage, the duty cycle and the magnitude of change in the threshold voltage. By lowering any of these parameters, reduction in change-in-threshold (Δ | V TH  | ) voltage will also be observed. Temperature is a function of power density and the rate at which heat is being removed from the system. Supply voltage can also be modified in order to control the power density because of its quadratic relationship, depending upon the workload for increased or decreased performance. Under lighter workloads the supply voltage can be lowered and conversely increased for demanding workloads.

Since, the PMOS only degrades when there is a negative gate to source (V GS ) voltage difference exist, then the ratio of negative V GS to positive V GS is referred as the duty cycle (β), it heavily impacts the change in threshold. For cache, this duty cycle is defined as a fraction of time cache is active as compared to idle (sleep) mode.

Figures 6.2 and 6.3 show the resulting (stress and recovery phases) shift in threshold voltage (Δ | V TH  | ) of a 32 nm and 45 nm PMOS transistor due to NBTI over a 5 years of time, respectively. The shifted threshold voltage is plotted for different duty cycles and V\({}_{GS} = -{V }_{DD} = -\)1 V ( − 0. 9 V for 32 nm) and T = 125 ∘ C. An elevated temperature is considered for simulation because NBTI has detrimental impact at higher temperature as compared to moderate one. Duty cycles for different cache configurations are explained and derived in Sect. 6.5. It can be seen from Figs. 6.2 and 6.3 that the duty cycle (β) has significant role in modulating the threshold voltage of a PMOS transistor. Higher duty cycle has more impact on shifting the resulting threshold voltage as compare to smaller duty cycle. In 5 years of time span, shift in threshold voltage for duty cycle of β = 0. 25 is 28 mV, however, for the same time period and duty cycle of β = 0. 75, shift in threshold voltage is 47 mV. Hence, it could be a good candidate to control the aging effects and its associated impacts on circuits and systems.

Fig. 6.2
figure 2

Shifted threshold voltage (Δ | V TH  | ) due to NBTI for a 32 nm technology node PMOS transistor versus time for different duty cycles (β)

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Fig. 6.3
figure 3

Shifted threshold voltage (Δ | V TH  | ) due to NBTI for a 45 nm technology node PMOS transistor versus time for different duty cycles (β)

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Two extreme duty cycles (β = 0. 25 and β = 0. 75) are considered to see the impact of NBTI on read SNM of a standard 6T SRAM bitcell. The lower duty cycle (β = 0. 25) corresponds to least NBTI impact, where SRAM is subjected to a minimum activity under the NBTI. However, higher duty cycle (β = 0. 75) corresponds to heavy NBTI impact on the SRAM bitcell when logic bit value ‘0’ being stored on average 75% of bit value. Figure 6.4 shows the NBTI impact (i.e. degradation of read SNM) on standard 6T SRAM bitcell for two different duty cycles β = 0. 25 and β = 0. 75. The effect of heavy duty cycle (i.e. β = 0. 75) is clearly visible which degrades the read SNM of a standard 6T SRAM bitcell about 10% as compared to its nominal configuration.

Fig. 6.4
figure 4

Standard 6T SRAM bitcell read static noise margin (SNM) degradation due to NBTI for β = 0. 25 and β = 0. 75

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In caches, there is a strong bias towards logic bit value ‘0’ being stored on average 75% of bit value for most of the time in data or instruction caches [21, 81]. By periodically inverting the contents of the cache and marking that the data is inverted this occupancy can be further reduced to 50%. Even with cache occupancy of logic bit value ‘0’ is 50%, then the PMOS devices are degrading but their degradation is occurring in a balanced fashion. Asymmetric SRAM bitcell based caches have been developed to take the advantage of skewed distribution of logic bit value ‘0’ in caches for leakage power reduction. However, asymmetry introduced by the dual-V TH devices seriously degrades the read SNM and make the SRAM bitcell more vulnerable to NBTI, process variations, soft errors and loss of stability, as shown in next section.

6.3 NBTI Model

To analysed the effect of NBTI on the degradation of SRAM read and write noise margins due to shift in threshold voltage of the PMOS transistors of a SRAM bitcell. The SRAM bitcells have been simulated considering the NBTI-induced shift in threshold voltage in each of the PMOS transistors. The NBTI degradation is modelled as a voltage source in series with PMOS gate [49, 91], as shown in Fig. 6.5. The shift in threshold voltage was calculated from the previously discussed R-D model for different duty cycles and time spans.

Fig. 6.5
figure 5

Simulation setup used for modelling the NBTI effect in PMOS transistor of a SRAM bitcell

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6.4 SRAM Bitcells Under NBTI

Figure 6.6 shows the symmetric standard 6T SARM bitcell and an asymmetric 6T SRAM bitcell for reduced leakage current is shown in Fig. 6.7. The aging phenomenon in different SRAM bitcells was introduced by incorporating the shift in threshold voltage of the PMOS devices, which was calculated from the R-D model discussed in the previous section and it was developed in MATLAB. Shift in threshold voltage was incorporated in different SRAM bitcells using the NBTI model as shown in Fig. 6.5. In symmetric 6T SRAM bitcell simulation setup, shown in Fig. 6.6, transistor M 1, M 2, M 4, M 5 and M 6 have nominal value of V TH models, while shifted Δ | V TH  | value due to NBTI is used for M 3 transistor model. Since, V GS of M3 is − V DD as a result it will experience the NBTI effect at large as compared to M 5.

Fig. 6.6
figure 6

Schematic diagram of a symmetric standard 6T SRAM bitcell

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Fig. 6.7
figure 7

Asymmetric 6T SRAM bitcell for reduced leakage current based on dual-V TH transistors (shaded transistors are high V TH )

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In asymmetric 6T SRAM bitcell, shown in Fig. 6.7 has three types of transistor models:

  • Transistors M 1 and M 6 have nominal value of V TH models,

  • Shifted Δ | V TH  | value due to NBTI is used for M 3 transistor model, and

  • Transistors M 2, M 4 and M 5 have high value of V TH models to reduce the leakage current.

All transistors in symmetric and asymmetric 6T SRAM bitcells are of minimum feature sized with bitcell ratio = 2 and \({M}_{1} = {M}_{2} = {M}_{3} = {M}_{5} =\) 45 nm/45 nm (32 nm/32 nm), and \({M}_{4} = {M}_{6}\, =\,\)90 nm/45 nm (64 nm/32 nm). In the read SNM free 6T (or 8T) SRAM bitcell, as shown in Fig. 6.9 regular-V TH and minimum feature sized transistors are used for simulation, while shifted Δ | V TH  | value due to NBTI is incorporated with M 3 transistor model.

Fig. 6.9
figure 9

Read SNM free 6T SRAM bitcell with shared read and write assist transistors (shaded) per word

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Figure 6.8 shows the Voltage Transfer Characteristics (VTCs) or butterfly curves of 6T (symmetric and asymmetric) and read SNM free 6T (or 8T) SRAM bitcells for 32 nm technology node with NBTI effect and the duty cycle β = 0. 25 for 5 years of time span. The butterfly curve of a symmetric 6T SRAM bitcell is almost symmetric and it has negligible effect of shifted threshold voltage due to NBTI. For asymmetric 6T SRAM bitcell, butterfly curve is not symmetric that is because of dual-V TH devices. However, shifted threshold voltage due to NBTI of transistor M 3 has less effect as compared to high-V TH devices (M 2, M 4 and M 5) used in the bitcell. In other words, low V TH devices age faster than the high V TH devices and NBTI V TH degradation is more significant at elevated temperature. For the read SNM free 6T (or 8T) SRAM bitcell, read SNM is equivalent to hold SNM or in other words an isolated read port held the data storage nodes unchanged. Hence, read SNM free 6T (or 8T) SRAM bitcell has better read SNM and 6T asymmetric SRAM bitcell has worst read SNM under NBTI.

Fig. 6.8
figure 8

Different SRAM bitcells butterfly curves for read SNM measurement under NBTI degradation

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The stability parameters (SNM and WNM) of 6T (symmetric and asymmetric) and read SNM free 6T (or 8T) SRAM bitcells are analyzed using HSPICE simulation in order to investigate the NBTI effects. Under NBTI pull-up (PMOS) transistors are more weakened, which skews the transfer characteristics of the inverter as a result degraded hold and read SNM. The write noise margin (WNM) of a standard 6T SRAM bitcell may improve or degrade depending upon the probability of stress. By weakening of the pull-up (PMOS) transistors due to NBTI may improve the WNM allowing ‘0’ to be written more easily, on the other hand a small noise may flip the bitcell content quickly.

The Static Noise Margin (SNM) obtained from the butterfly curve is used for measuring the read and hold stability. The SNM is estimated graphically as the length of a side of the largest square that can be embedded inside the lobes of the butterfly curve [95]. While the write stability (WNM) is measured using the write trip point, defined as the minimum amount of voltage needed on the bitline to flip the bitcell content [35].

Tables 6.1 and 6.2 show the degradation and recovery in stability parameters, respectively, for the 6T (symmetric and asymmetric) and read SNM free 6T (or 8T) SRAM bitcell caches. Degradation in read SNM and WNM are calculated by simulating the SRAM bitcells for the shifted value of threshold voltage due to NBTI after 5 years of time for different duty cycles. Elevated temperature 125 ∘ C has been considered for the simulation as NBTI is more pronounced at higher temperature. The percentage of recovery in SNM and WNM are calculated by incorporating the dynamically recovered threshold voltage for β = 0. 25 in the SRAM bitcells, simulation results for different SRAM bitcells are tabulated in Table 6.2.

Table 6.1 Read SNM and WNM degradation due to NBTI for 32 nm technology at 125 ∘ C
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Table 6.2 Recovery of read SNM and WNM for 32 nm technology at 125 ∘ C and duty cycle (β) = 0.25
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The amount of degradation in the read SNM and WNM is approximately 10% for both symmetric and asymmetric 6T SRAM bitcells after 5 years of time span. While there is a 28.3% reduction in read SNM for the asymmetric 6T SRAM bitcell as compared to symmetric 6T SRAM bitcell, as shown in Table 6.1. This drastic reduction in read SNM is mainly due to asymmetry introduced by the dual-V TH devices used in the bitcell, in order to minimize the leakage current. Also an opposite trend of WNM is observed, WNM of the initial (t = 0) SRAM bitcell is lower than the stressed (t = 5 years) SRAM bitcell, because of increase in trip-point of inverter (M3, and M4). Therefore, higher voltage is needed at the bitlines to write into the SRAM bitcells due to aging effect.

Recovery in the read SNM for different SRAM bitcells are almost equal, as shown in Table 6.2. However, recovery in WNM for asymmetric 6T SRAM bitcell is slightly higher than the symmetric 6T SRAM bitcell. Since, asymmetric SRAM bitcell consists of high V TH devices, which has less impact of NBTI as compared to low V TH devices used in symmetric SRAM bitcell, hence, higher recovery in WNM is observed.

6.5 Leakage Energy Saving Techniques in Caches

With increasing device density, lower supply voltage and threshold voltage, the trend of energy optimization is shifted from dynamic to leakage energy. Leakage energy is dominating in the dense cache memories that occupy a major portion of a die. Many techniques have been proposed in the past to reduce leakage during idle mode by switching off the supply voltage, such as, gated-V DD to dynamically shutdown cache blocks [54, 118] and used in conjunction with software to remove the dead objects [26]. However, dynamically shutting down the cache blocks results in state of the cache memory being lost (state-destroying). Various alternate state-preserving techniques have also been proposed in the recent past for leakage savings [70, 106]. The choice between state-preserving and state-destroying depends on the additional overheads needed for restoring the lost state from the other level of memory hierarchy.

By lowering the supply voltage dynamically (gated-V DD ) of the cache blocks, leakage energy can be saved. If the path to V DD or ground is completely cut-off then the state of the cache is lost and this is considered as a state destroying mode. Otherwise, if the supply voltage is lowered but the SRAM bitcells are still able to maintain their state then this is considered as a state preserving mode and the cache is termed to be in a sleep state. An earlier work [69] had considered a number of state preserving and state destroying strategies for leakage savings and focused on exploiting the data duplication present in an on-chip L1-L2 cache hierarchy (which consists of an L1 instruction cache, an L1 data cache, and a unified L2 cache). In general, in an L1-L2 cache hierarchy, the data present in L1 is also contained in L2, hence, leakage energy can be saved by keeping only one active copy of the data. The five main strategies, that exploit the state-preserving and state-destroying leakage optimization mechanisms are as follows [69]:

  • CONSERVATIVE: When a block in L1 is written to, then the corresponding sub-block in L2 is fully turned off in a state destroying mode. Since the block in L1 is dirty then the block in L2 is dead and can be safely deactivated. Since, instructions are not written to, this strategy cannot be optimized.

  • SPECULATIVE I: When a block is brought from L2 to L1, the block in L1 is put in a state-preserving mode immediately. It does not wait for the L1 block to become dirty nor does it lose data. If the evicted block had become dirty then the block in L2 is reactivated and written into.

  • SPECULATIVE II: Similar to Speculative I but instead the L2 block is put into the state destroying mode instead of sleep mode.

  • SPECULATIVE III: This is similar to Speculative I, but the block in L2 is speculatively woken up when the L1 block is evicted.

  • SPECULATIVE IV: This is similar to Speculative I, except the L2 block is reactivated and written back, whenever the corresponding L1 cache block needs to be replaced.

6.5.1 Leakage Energy Saving Cache Configurations

Media and array dominated application benchmarks such as Media-Bench, Spec and Perfect Club are used for cycle-accurate simulations, under different power saving cache strategies to determine the leakage energy savings. The leakage energy saved under these cache strategies was used to calculate the average inactive time experienced by the cache blocks. Based on the average inactive time, the duty cycles (β) are derived and following different cases (cache configurations) are formed:

  • CASE 1: Exploits the skewed distribution of ‘0’ with average occupancy of 75% of the time. Due to the symmetric nature of SRAMs if one of the PMOSs has a duty cycle of 0.75 then the other has a duty cycle of 0.25.

  • CASE 2: Under normal cache with an additional record stating if the value is inverted or not, or with periodic inversions the duty cycle will approach to 0.5 equalizing the degradation on both the PMOS transistors.

  • CASE 3: Extends CASE 2 and incorporates the Conservative strategy of disabling cache blocks.

  • CASE 4: Employs sleep mode of cache blocks when the block is written into L1. It attempts to speculatively wake up the L2 block before it is needed.

  • CASE 5: It is similar to CASE 4, but it only wakes up the block when it is needed.

  • CASE 6: It combines the sleep mode with the disabled mode using a timer that if it expires switches the cache block-off instead of sleeping.

Table 6.3 summarizes different cases formed on the basis of state-preserving and state-destroying leakage saving strategies discussed above, and their corresponding duty cycles in column 2. The NBTI induced shift in threshold voltage (Δ | V TH  | ) for 32 nm and 45 nm technology node PMOS transistors after 5 years is estimated using the model described in Eqs. 6.1, considering their respective duty cycles (β). We use PTM 32 nm and 45 nm technology models [88], with following parameters provided in the Table 6.4.

Table 6.3 Drived duty cycles and resulting change (or shift) in threshold voltage for different cases (or cache configurations)
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Table 6.4 PTM Technology model parameters used for simulation of different SRAM bitcells and cache configurations
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The PMOS transistor models with shifted threshold voltage due to NBTI for different duty cycles are incorporated in HSPICE net list to simulate different SRAM bitcell based cache configurations for their stability parameters, leakage current measurement and process variation analysis.

6.6 Stability Recovery Under Different Cache Configurations

In order to demonstrate the effectiveness of dynamically recovering the change in threshold voltage (V TH ) under different cache configurations, formed on the basis of leakage energy saving cache strategies, recovery in stability parameters read SNM and WNM is measured for different SRAM bitcells.

6.6.1 Read SNM Recovery

As it is shown in the previous Chaps. 1 and 2 that the read SNM is one of the critical stability parameters of a SRAM bitcell in nano-regime. It is crucial for a successful implementation of the reliable and high performance caches. The impact of NBTI due to aging makes it more challenging. Figures 6.10 and 6.11 show the recovery in read SNM for 32 nm and 45 nm technology nodes respectively, at 70 ∘ C and 125 ∘ C for different SRAM bitcells based cache configurations. Recovery in read SNM for different SRAM cache configurations varies from 38% for cache configuration CASE-1 to 66% for cache configuration CASE-6. There is a slight increase in recovery of read SNM at higher temperature.

Fig. 6.10
figure 10

Percentage (%) of recovery of read static noise margin (SNM) for different cache configurations based on 32 nm node SRAM bitcells (a) Recovery in read SNM at 70 ∘ C (b) Recovery in read SNM at 125 ∘ C

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Fig. 6.11
figure 11

Percentage (%) of recovery of read static noise margin (SNM) for different cache configurations based on 45 nm node SRAM bitcells. (a) Recovery in read SNM at 70 ∘ C. (b) Recovery in read SNM at 125 ∘ C

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As we have seen in Sect. 6.2 that duty cycle β has significant role in modulating the shift in threshold voltage due to aging, which is also visible from the percentage of recovery of read SNM for different SRAM bitcell based cache configurations. Increased rate of recovery of SNM in different SRAM caches is specifically seen for lower duty cycles. It is mainly because of less impact of NBTI under lower duty cycles, or in other words, cache blocks are kept in the state-destroying mode for regular interval of time. Therefore, CASE-6 has least impact of NBTI or has better capability of dynamically recovering the shifted threshold voltage due to NBTI. Hence, it can be a good candidate of cache configuration, where reliability and life span is a major concern.

6.6.2 WNM Recovery

A similar trend has also been observed in the recovery of WNM for different SRAM bitcells based cache configurations. However, rate of recovery of WNM for asymmetric 6T SRAM bitcell caches is slightly lower than the symmetric 6T SRAM bitcells based caches, as shown in Figs. 6.12 and 6.13 for 32 nm and 45 nm nodes, respectively. While the rate of recovery of WNM of the SNM free 6T (or 8T) SRAM has almost equivalent to symmetric 6T SRAM, since write operation in the SNM free 6T (or 8T) SRAM will takes place in similar fashion of symmetric 6T, assuming that the regular V TH devices are used.

Fig. 6.12
figure 12

Percentage (%) of recovery of write noise margin (WNM) for different cache configurations based on 32 nm node SRAM bitcells. (a) Recovery in write noise margin (WNM) at 70 ∘ C. (b) Recovery in write noise margin (WNM) at 125 ∘ C

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Fig. 6.13
figure 13

Percentage (%) of recovery of write noise margin (WNM) for different cache configurations based on 45 nm node SRAM bitcells. (a) Recovery in write noise margin (WNM) at 70 ∘ C. (b) Recovery in write noise margin (WNM) at 125 ∘ C

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Increased rate of recovery of WNM is also observed, in particular for lower duty cycles in different SRAM bitcells based cache configurations. It is purely because of lower duty cycles. It can be seen from Figs. 6.12 and 6.13, that the CASE-6 has least impact of NBTI or in other words it has better capability of dynamically recovering the shifted threshold voltage due to NBTI.

6.7 Effect of NBTI Under Process Variation

Increasing sensitivity of variation in design and process parameters, particularly threshold voltage leads to a greater loss of parametric yield with respect to SRAM bitcell noise margins or stability parameters [10]. The effect of NBTI has direct impact on the PMOS device threshold voltage as a result SRAM bitcells may be more susceptible to parametric failure due to aging effect. As it is evident from the previous section that read SNM and WNM follow almost the similar trend, hence, the study of process variations on leakage current is considered in this section for different cache configurations. Leakage current has strong exponential dependence on threshold voltage. In order to investigate the effect of NBTI along with process variations on read SNM and leakage current, 1,000 Monte Carlo simulations are preformed for each cache configuration, it is assumed that a 15% variation in V TH with 3σ as an independent random variable for all the transistors in 6T and SNM free 6T (or 8T) SRAM bitcells with Gaussian distribution.

6.7.1 Read SNM Distribution Under Process Variation

Figures 6.14 and 6.15 show the read SNM distribution of 32 nm and 45 nm technology nodes, respectively, at 125 ∘ C temperature for different SRAM bitcells. Degradation in mean read SNM due to NBTI after 5 years of time is clearly visible. The effect of process variations along with NBTI is more dominant in 32 nm node as compared to 45 nm technology node, which is quite obvious and expected, since smaller feature sized devices are more susceptible to process variations. However, asymmetric 6T SRAM bitcell shows large standard deviation in read SNM as compared to its counterpart symmetric 6T and the SNM free 6T (or 8T) SRAM bitcells for both the technology nodes. Furthermore, higher mean value of read SNM in the SNM free 6T (or 8T) SRAM bitcell is achieved, as shown in Figs. 6.14 and 6.15, this improvement in read SNM is mainly due to the isolated read port.

Fig. 6.14
figure 14

Read SNM distribution of different SRAM bitcells for 32 nm technology node

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Fig. 6.15
figure 15

Read SNM distribution of different SRAM bitcells for 45 nm technology node

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6.7.2 Leakage Current Distribution Under Process Variations

Figures 6.16 and 6.17 show the leakage current distribution of 32 nm and 45 nm technology nodes respectively at 125 ∘ C temperature for different SRAM bitcell configurations. It is seen from Figs. 6.16 and 6.17 that the leakage current follows the log-normal distribution because of its exponential dependence with the threshold voltage. Also there is significant reduction in mean leakage current for asymmetric 6T SRAM bitcell as compared to symmetric 6T and the SNM free 6T (or 8T) bitcells, this is due to dual-V TH devices used in the asymmetric 6T SRAM bitcell. However, the SNM free 6T (or 8T) bitcell has higher mean leakage current than 6T (symmetric and asymmetric), since it has an extra leakage path from the read port.

Fig. 6.16
figure 16

Leakage current distribution of different SRAM bitcells for 32 nm technology node

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Fig. 6.17
figure 17

Leakage current distribution of different SRAM bitcells for 45 nm technology node

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6.8 Summary

In this chapter, a detailed examination of the effect of NBTI along with process variations on different SRAM bitcells in low power cache configurations, is presented. The impact of NBTI is studied for different SRAM bitcells namely the 6T (symmetric and asymmetric) and the read SNM free 6T with 32 nm and 45 nm technology nodes at different temperatures. It is observed that the combination of sleeping modes with complete shut-off of the cache when not required (i.e. β = 0. 25) provides the best recovery of ∼ 66%. Hence, this cache configuration is a good candidate for applications where reliability and life span is a major concern. Also the use of 6T asymmetric bitcells is not advisable only just because of saving in leakage energy but due to poor read SNM. In particular, for reliable applications because of lowest read SNM and higher susceptibility to process variation. However, the read SNM free 6T SRAM bitcell based cache configurations are best suited for reliable applications, since, this bitcell is less vulnerable to process variations and yields the higher read SNM.