Abstract
With increasing application complexity and improvements in process technology, multi-processor systems-on-chip (MPSoC) with tens to hundreds of cores on a chip are being realized today. While computational cores have become faster with each successive technology generation, communication between them has not scaled well, and has become a bottleneck that limits overall chip performance. On-chip optical interconnects are a promising development to overcome this bottleneck by replacing electrical wires with optical waveguides. In this chapter we describe an optical ring bus (ORB) based hybrid opto-electric on-chip communication architecture for the next generation of heterogeneous MPSoCs. ORB uses an optical ring waveguide to replace global pipelined electrical interconnects while preserving the interface with today’s bus protocol standards such as AMBA AXI3. The proposed ORB architecture supports serialization of uplinks/downlinks to optimize communication power dissipation. We present experiments to show how ORB has the potential to reduce transfer latency (up to 4.7×), and lower power consumption (up to 12×) compared to traditionally used pipelined, all-electrical, bus-based communication architectures, for the 22 nm technology node.
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Pasricha, S., Dutt, N.D. (2013). On-Chip Optical Ring Bus Communication Architecture for Heterogeneous MPSoC. In: O'Connor, I., Nicolescu, G. (eds) Integrated Optical Interconnect Architectures for Embedded Systems. Embedded Systems. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-6193-8_5
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DOI: https://doi.org/10.1007/978-1-4419-6193-8_5
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