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Designing Embedded Processors pp 131–155Cite as

Power Optimisation Strategies Targeting the Memory Subsystem

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Power optimisations targeting the memory subsystem have received considerable attention in recent years because of the dominant role played by memory in the overall system power. The more complex the application, the greater the volume of instructions and data involved, and hence, the greater the significance of issues involving power-efficient storage and retrieval of these instructions and data. In this chapter we give a brief overview of how memory architecture and accesses affect system power dissipation, and some recent proposals on reducing memory-related power through diverse mechanisms: optimisations of the traditional cache memory system, architectural innovations targeting application specific designs, compiler optimisations, and other techniques.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology, 110016, Hauz Khas, New Delhi, India

    Preeti Ranjan Panda

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  1. Preeti Ranjan Panda
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Editors and Affiliations

  1. University of Karlsruhe (TH), Zirkel 2, D-76131, Karlsruhe, Germany

    Jörg Henkel

  2. The University of New South Wales, 2033, NSW, Australia

    Sri Parameswaran

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Panda, P.R. (2007). Power Optimisation Strategies Targeting the Memory Subsystem. In: Henkel, J., Parameswaran, S. (eds) Designing Embedded Processors. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-5869-1_6

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  • DOI: https://doi.org/10.1007/978-1-4020-5869-1_6

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