Abstract
This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying reconfigurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers [292] and the High-Level Compiler from Nallatech [223], both of which support the mapping of programs written in a subset of the C programming language to FPGAs.
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© 2008 Springer Science+Business Media, LLC
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Cardoso, J.M.P., Diniz, P.C. (2008). Compilers for Reconfigurable Architectures. In: Compilation Techniques for Reconfigurable Architectures. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-09671-1_6
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DOI: https://doi.org/10.1007/978-0-387-09671-1_6
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Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-09670-4
Online ISBN: 978-0-387-09671-1
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