Abstract
The increasing demand of networking applications has imposed a new category of electronic circuits that integrate powerful CPU processing, networking and system support functions in a single, low cost chip. These integrated circuits, called Network Processors, are optimized for tasks such as access protocol implementation, data queuing and forwarding, traffic shaping and Quality of Service (QoS) support. This paper presents the use of Field Programmable System Level Integrated Circuits that combine the flexibility of programmable cores and the high performance of dedicated hardware, to implement network processors used for medium access protocols.
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References
Nicholas, Cravotta, Network processors: The Sky’s the Limit, EDN Magazine, November 1999, pages 108–119.
ATMEL, AT94 Series Field Programmable System Level Integrated Circuit, Advance Information.
Marios Iliopoulos, Theodore Antonakopoulos, A Methodology of Implementing Medium Access Protocols Using a General Parameterized Architecture, 11th IEEE International Workshop on Rapid System Prototyping, June 2000, France.
ANSI/IEEE Std 802.3-1996: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications
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© 2000 Springer-Verlag Berlin Heidelberg
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Iliopoulos, M., Antonakopoulos, T. (2000). Reconfigurable Network Processors Based on Field Programmable System Level Integrated Circuits. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_5
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DOI: https://doi.org/10.1007/3-540-44614-1_5
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