Abstract
The eXtreme Processing Platform (XPP) is a coarse-grained dynamically reconfigurable architecture. Its advanced reconfiguration features make feasible the configure-execute paradigm, the natural paradigm of dynamically reconfigurable computing. This chapter presents a compiler aiming to program the XPP using a subset of the C language. The compiler, apart from mapping the computational structures onto the available resources on the device, splits the program in temporal sections when it needs more resources than the physically available. In addition, since the execution of the computational structures in a configuration needs at least two stages (e.g., configuring and computing), a scheme to split the program such that the reconfiguration overheads are minimized, taking advantage of the overlapping of the execution stages on different configurations is presented.
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References
R. Hartenstein, “A Decade of Reconfigurable Computing: a Visionary Retrospective,” in Proc. Design, Automation and Test in Europe (DATE'01), 2001, pp. 642–649.
V. Baumgarte, et al., “PACT XPP—A Self-Reconfigurable Data Processing Architecture,” in The Journal of Supercomputing, Kluwer Academic Publishers, Sept. 2003, pp. 167–184.
J. M. P. Cardoso, and M. Weinhardt, “XPP-VC: A C Compiler with Temporal Partitioning for the PACT-XPP Architecture,” in Proc. 12th Int'l Conference on Field Programmable Logic and Applications (FPL'02), LNCS 2438, Springer-Verlag, 2002, pp. 864–874.
J. M. P. Cardoso, and M. Weinhardt, “From C Programs to the Configure-Execute Model,” in Proc. Design, Automation and Test in Europe (DATE'03), Munich, Germany, March 3–7, 2003, pp. 576–581.
M. Weinhardt, and W. Luk, “Pipeline Vectorization,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Feb. 2001, pp. 234–248.
R. Hartenstein, R. Kress, and H. Reining, “A Dynamically Reconfigurable Wave front Array Architecture for Evaluation of Expressions,” in Proc. Int'l Conference on Application-Specific Array Processors (ASAP'94), 1994.
SUIF Compiler system, “The Stanford SUIF Compiler Group,” http://suif.stanford.edu
S. S. Muchnick, Advanced Compiler Design and Implementation. Morgan Kaufmann Publishers, Inc., San Francisco, CA, USA, 1997.
I. Page, and W. Luk, “Compiling occam into FPGAs,” in FPGAs, Will Moore and Wayne Luk, eds., Abingdon EE & CS Books, Abingdon, England, UK, 1991, pp. 271–283.
M. Gokhale, and A. Marks, “Automatic Synthesis of Parallel Programs Targeted to Dynamically Reconfigurable Logic Array,” in Proc. 5th Int'l Workshop on Field Programmable Logic and Applications (FPL'95), LNCS, Springer-Verlag, 1995, pp. 399–408.
J. M. P. Cardoso, and H. C. Neto, “Compilation for FPGA-Based Reconfigurable Hardware,” in IEEE Design & Test of Computers Magazine, March/April, 2003, vol. 20, no. 2, pp. 65–75.
S. Goldstein, et al., “PipeRench: A Reconfigurable Architecture and Compiler,” in IEEE Computer, Vol. 33, No. 4, April 2000, pp. 70–77.
I. Ouaiss, et al., “An Integrated Partioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures,” in Proc. 5th Reconfigurable ArchitecturesWorkshop (RAW'98), Orlando, Florida, USA, March 30, 1998, pp. 31–36.
S. Ganesan, and R. Vemuri, “An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement,” in Proc. Design, Automation & Test in Europe (DATE'00), Paris, France, March 27–30, 2000, pp. 320–325.
G. Venkataramani, et al., “Automatic compilation to a coarse-grained reconfigurable system-on-chip,” in ACM Transactions on Embedded Computing Systems (TECS), Vol. 2, Issue 4, November 2003, pp. 560–589.
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Cardoso, J.M., Weinhardt, M. (2005). Compilation and Temporal Partitioning for a Coarse-grain Reconfigurable Architecture. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_9
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DOI: https://doi.org/10.1007/1-4020-3128-9_9
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