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Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits pp 5–14Cite as

Sources of Variation

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Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 41))

Abstract

Variations in process, supply voltage and temperature (PVT) have always been an issue in Integrated Circuit (IC) Design. In digital circuits, PVT fluctuations affect the switching speed of the transistors and thus the timing of the logic. To guarantee fault-free operation for a specified clock frequency, IC designers have to quantify these uncertainties and account for them adequately. This is typically done by guard-banding, i.e. adding sufficient voltage safety margin to ensure proper working even under worst-case condition.

At recent technology nodes, transistor characteristics are more and more influenced also by aging effects. These wear-out effects, namely hot carrier injection (HCI) and bias temperature instability (BTI), degrade the drive current of transistors during use. Hence, further safety margin has to be added, dependent on the specified lifetime of a product.

The following four sections will give an overview of process, voltage and temperature variations as well as aging (PVTA). The necessary fundamentals are briefly explained and the impact on circuit-level timing is discussed.

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Notes

  1. 1.

    The derivation for \(\sigma_{\mathit{t,d}}\) can be found in the Appendix.

References

  1. The International Technology Roadmap for Semiconductors (ITRS): Design (2011), http://www.itrs.net/Links/2011ITRS/2011Chapters/2011Design.pdf

  2. S.K. Saha, Modeling process variability in scaled CMOS technology. IEEE Des. Test Comput. 27(2), 8–16 (2010)

    Article  Google Scholar 

  3. P. Bai, C. Auth, S. Balakrishnan, M. Bost, R. Brain, V. Chikarmane, R. Heussner, M. Hussein, J. Hwang, D. Ingerly, R. James, J. Jeong, C. Kenyon, E. Lee, S.-H. Lee, N. Lindert, M. Liu, Z. Ma, T. Marieb, A. Murthy, R. Nagisetty, S. Natarajan, J. Neirynck, A. Ott, C. Parker, J. Sebastian, R. Shaheed, S. Sivakumar, J. Steigerwald, S. Tyagi, C. Weber, B. Woolery, A. Yeoh, K. Zhang, M. Bohr, A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57μm2 SRAM cell, in Proceedings of the IEEE International Electron Devices Meeting (IEDM) (2004), pp. 657–660

    Google Scholar 

  4. A. Asenov, S. Kaya, A.R. Brown, Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness. IEEE J. Solid-State Circuits 50(5), 1254–1260 (2003)

    Google Scholar 

  5. C.H. Diaz, H.-J. Tao, Y.-C. Ku, A. Yen, K. Young, An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling. IEEE J. Solid-State Circuits 22(6), 287–289 (2001)

    Google Scholar 

  6. K.J. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, K. Zawadzki, Managing process variation in Intel’s 45nm CMOS technology. Intel Technol. J. 12, 93–109 (2008)

    Google Scholar 

  7. A. Asenov, S. Kaya, J.H. Davies, Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations. IEEE J. Solid-State Circuits 49(1), 112–119 (2002)

    Google Scholar 

  8. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma, A. Maheshwari, S. Mudanai, Process technology variation. IEEE Trans. Electron Devices 58(8), 2197–2208 (2011)

    Article  ADS  Google Scholar 

  9. M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989)

    Article  Google Scholar 

  10. T. Sakurai, A.R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. IEEE J. Solid-State Circuits 25(2), 584–594 (1990)

    Article  Google Scholar 

  11. J. Choi, C.-Y. Cher, H. Franke, H. Hamann, A. Weger, P. Bose, Thermal-aware task scheduling at the system software level, in Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (2007), pp. 213–218

    Google Scholar 

  12. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, Parameter variations and impact on circuits and microarchitecture, in Proceedings of the Design Automation Conference (DAC) (2003), pp. 338–342

    Google Scholar 

  13. A. Bravaix, V. Huard, D. Goguenheim, E. Vincent, Hot-carrier to cold-carrier device lifetime modeling with temperature for low power 40nm Si-bulk NMOS and PMOS FETs, in Proceedings of the IEEE International Electron Devices Meeting (IEDM) (2011)

    Google Scholar 

  14. B. Kaczer, S. Mahato, V.V. de Almeida Camargo, M. Toledano-Luque, P.J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth, G. Groeseneken, Atomistic approach to variability of bias-temperature instability in circuit simulations, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2011), pp. 915–919

    Google Scholar 

  15. T. Grasser, H. Reisinger, P. Wagner, F. Schanovsky, W. Goes, B. Kaczer, The time dependent defect spectroscopy (TDDS) for the characterization of the bias temperature instability, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 16–25

    Google Scholar 

  16. H. Reisinger, T. Grasser, K. Hofmann, W. Gustin, C. Schlünder, The impact of recovery on BTI reliability assessments, in Proceedings of the IEEE International Integrated Reliability Workshop Final Report (IRW) (2010), pp. 12–16

    Google Scholar 

  17. F.R. Chouard, C. Werner, D. Schmitt-Landsiedel, M. Fulde, A test concept for circuit level aging demonstrated by a differential amplifier, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 826–829

    Google Scholar 

  18. S. Drapatz, K. Hofmann, G. Georgakos, D. Schmitt-Landsiedel, Impact of fast-recovering NBTI degradation on stability of large-scale SRAM arrays, in Proceedings of the IEEE European Solid-State Device Research Conference (ESSDERC) (2010), pp. 146–149

    Google Scholar 

  19. T. Grasser, P.-J. Wagner, H. Reisinger, T. Aichinger, G. Pobegen, M. Nelhiebel, B. Kaczer, Analytic modeling of the bias temperature instability using capture/emission time maps, in Proceedings of the IEEE International Electron Devices Meeting (IEDM) (2011)

    Google Scholar 

  20. H. Reisinger, T. Grasser, W. Gustin, C. Schlünder, The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress, in Proceedings of the IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 7–15

    Google Scholar 

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Authors and Affiliations

  1. Electrical Engineering, Technische Universität München, Munich, Germany

    Martin Wirnshofer

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  1. Martin Wirnshofer
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Wirnshofer, M. (2013). Sources of Variation. In: Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Series in Advanced Microelectronics, vol 41. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6196-4_2

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  • DOI: https://doi.org/10.1007/978-94-007-6196-4_2

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-6195-7

  • Online ISBN: 978-94-007-6196-4

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