Abstract
The industry is adapting multi-core microprocessor hardware in various application areas. The available additional calculation power accelerates the change from hardware into software based solutions.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
A. Shappir, E. Lusky, G. Cohen, B. Eitan, NROM window sensing for 2 and 4-bits per cell products, in NVSMWS, Monterey, CA, (2006)
N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, K. Kanebako, S. Yoshikawa, H. Tabata, A. Inoue, T. Takahashi, T. Shano, Y. Komatsu, K. Nagaba, M. Kosakai, N.Motohashi, A 70 nm 16 Gb 16-level-cell NAND flash memory. IEEE J. Solid-State Circuits 43, 929–937 (2008)
C. Trinh, N. Shibata, T. Nakano, M. Ogawa, J. Sato, Y. Takeyama, K. Isobe, B. Le, F. Moogat, N. Mokhlesi, K. Kozakai, P. Hong, T. Kamei, K. Iwasa, J. Nakai, T. Shimizu, M. Honma, S. Sakai, T. Kawaai, S. Hoshi, J. Yuh, A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS, in ISSCC, Digest of Technical Papers, pp. 246–247, San Francisco, 2009
M. Deutscher, Fusion-io’s flash NAS software makes your servers run 25X faster. SiliconAngle. 03 Aug 2012
M. Feldman, HPCWire. 22 Jan 2010. http://www.hpcwire.com/hpcwire/2010-01-22/govt_brews_national_cloud_for_science.html. Zugriff am 17 Juni 2011
Micron Technology, Inc., Product Brief LPDDR2-PCM and Mobile LPDDR2 121-Ball MCP. Micron Product Specification, Boise, 2012
M. Miranda, When every atom counts—as transistors shrink, the problem of chip variability grows. IEEE Spectrum, 30–35 (July 2012)
H. Tanaka, M. Kido, K. Yahashi, M. Oomura, R. Katsumata, M. Kito, Y. Fukuzumi, M. Sato, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, A. Nitayama, Bit cost scalable technology with punch and plug process for ultra high density flash memory, in IEEE Symposium on VLSI Technology, 2007, pp. 14–15, Kyoto (2007)
A. Nitayama, H. Atochi, Bit cost scalable (BiCS) flash technology for future ultra high density storage devices, in VLSI Technology Systems and Applications (VLSI-TSA), pp. 130–131, Hsinchu (2010)
C. Kim, J. Ryu, T. Lee, H. Kim, J. Lim, J. Jeong, S. Seo, H. Jeon, B. Kim, I. Lee, D. Lee, P. Kwak, S. Cho, Y. Yim, C. Cho, W. Jeong, K. Park, J.-M. Han, D. Song, K. Kyung, A 21 nm High Performance 64 GbMLC NAND flash memory With 400MB/s asynchronous toggle DDR interface. IEEE J. Solid-State Circuits 47, 981–989 (2012)
K. Kanda, N. Shibata, T. Hisada, K. Isobe, M. Sato, Y. Shimizu, T. Shimizu, T. Sugimoto, T. Kobayashi, N. Kanagawa, Y. Kajitani, T. Ogawa, K. Iwasa, M. Kojima, T. Suzuki, Y. Suzuki, S. Sakai, T. Fujimura, Y. Utsunomiya, T. Hashimoto, A 19 nm 112.8 mm2 64 Gb multi-level flash memory with 400 Mbit/sec/pin 1.8 V toggle mode interface. IEEE J. Solid-State Circ. 48, 1–9 (2013)
T. Maeda, K. Itagaki, T. Hishida, R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, H. Aochi, Y. Iwata, Multi-stacked 1G cell/layer Pipe-shaped BiCS flash memory, in Symposium on VLSI Circuits, 2009, pp. 22–23, Kyoto (2009)
R. Katsumata, M. Kito, Y. Fukuzumi, M. Kido, H. Tanaka, Y. Komori, M. Ishiduki, J. Matsunami, T. Fujiwara, Y. Nagata, L. Zhang, Y. Iwata, R. Kirisawa, H. Aochi, A. Nitayama, Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices, in Symposium on VLSI Technology, 2009, pp. 136–137, Honolulu (2009)
J. Jang, H.-S. Kim, W. Cho, H. Cho, J. Kim, S. I. Shim, Y. Jang, J.-H. Jeong, B.-K. Son, D. W. Kim, Kihyun, J.-J. Shim, J. Lim, K.-H. Kim, S. Y. Yi, J.-Y. Lim, D. Chung, H.-C. Moon, Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory, in Symposium on VLSI Technology, 2009, pp. 192–193, Honolulu (2009)
Y. Yanagihara, K. Miyaji, K. Takeuchi, Control gate length, spacing and stacked layer number design for 3D-stackable NAND flash memory, in 4th IEEE International Memory Workshop (IMW), 2012, Milan (2012)
C. Friederich, M. Specht, T. Lutz, F. Hofinann, L. Dreeskornfeld, W. Weber, J. Kretz, T. Melde, W. Rosner, E. Landgraf, J. Hartwich, M. Stadele, L. Risch, D. Richter, Multi-level p+ tri-gate SONOS NAND string arrays, in IEDM Technical Digest, pp. 1–4, Washington, 2006
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2014 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Richter, D. (2014). System Optimization Based on Performance Indicator Models. In: Flash Memories. Springer Series in Advanced Microelectronics, vol 40. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6082-0_7
Download citation
DOI: https://doi.org/10.1007/978-94-007-6082-0_7
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-6081-3
Online ISBN: 978-94-007-6082-0
eBook Packages: EngineeringEngineering (R0)