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Low-Density Parity-Check (LDPC) Codes

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Inside Solid State Drives (SSDs)

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 37))

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Abstract

In this chapter, low-density parity-check (LDPC) codes, a class of powerful iteratively decodable error correcting codes, are introduced. The chapter first reviews some basic concepts and results in information theory such as Shannon’s channel capacity and channel coding theorem. It then overviews the Flash memory channel model. Finally, it addresses LDPC codes describing both their structure and efficient implementation, and their decoding algorithms. Simulation results are also provided.

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Notes

  1. 1.

    The capacity of the BSC only depends on the crossover probability and not on the values assumed by X and Y.

  2. 2.

    For unstructured ensemble, the minimum variable and check nodes are usually set to 2. The reason for this choice is out of the scope of this chapter.

  3. 3.

    The described protograph-based technique is not the only one to construct good QC-LDPC codes. Another possible approach is based on Euclidean and projective finite geometries [5, 27].

  4. 4.

    The words “horizontal” and “vertical” remind us that the check nodes and the variable nodes are associated with the rows and the columns of the parity-check matrix, respectively.

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Acknowledgment

The author wishes to thank Prof. M. Chiani (University of Bologna) and Dr. G. Liva (DLR) for their useful feedback. He also wishes to thank Ing. R. Micheloni and A. Marelli (IDT Italy) for their careful proof check of this chapter.

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  1. Department of Electrical, Electronic and Information Engineering G. Marconi (DEI), University of Bologna, Cesena, Italy

    E. Paolini

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Paolini, E. (2013). Low-Density Parity-Check (LDPC) Codes. In: Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-5146-0_11

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  • DOI: https://doi.org/10.1007/978-94-007-5146-0_11

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