Abstract
Partial Reconfiguration (PR) is the ability to change a portion (the reconfigurable partition) of the device without disturbing the normal operation of the rest (the static partition). A typical PR application is a reconfigurable coprocessor which switches the configuration of the reconfigurable partition at run-time when required by the application. The main advantage is the ability to map different coprocessor configurations in the reconfigurable partition in a time-multiplexed way, reducing the required area.
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References
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© 2012 Springer Science+Business Media Dordrecht
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Deschamps, JP., Sutter, G.D., Cantó, E. (2012). Partial Reconfiguration on Xilinx FPGAs. In: Guide to FPGA Implementation of Arithmetic Functions. Lecture Notes in Electrical Engineering, vol 149. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2987-2_16
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DOI: https://doi.org/10.1007/978-94-007-2987-2_16
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