Abstract
This chapter introduces a methodology for fast and efficient Design Space Exploration during High Level Synthesis. Motivated by the fact that higher quality design solutions are delivered when a larger number of parameters are explored, we study an augmented instance of the design space considering the combined impact of loop-unrolling, operation chaining and resource allocation onto the final datapath. We propose an iterative design space partitioning exploration strategy based on the synergy of an exhaustive traversal together with an introduced heuristic one. The introduced heuristic is based on a gradient-based pruning technique which efficiently evaluates large portions of the solution space in a quick manner. We show that the proposed exploration approach delivers high quality results, with considerable reductions of the exploration’s runtime in respect to the fully exhaustive approach.
This research is partially supported by the E.C funded program MOSART IST-215244,Website:http://www.mosart-project.org/.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
International Sematech (2005) International Technology Roadmap for Semiconductors, http://www.sematech.org
Coussy P, Morawiec A (2008) High-level synthesis: from algorithm to digital circuit. Springer, Berlin
Gries M (2004) Methods for evaluating and covering the design space during early design development. Integr VLSI J 38(2):131–183
Pareto V (2008) Manuale di Economia Politica. Picola Biblioteca Scientifica, Milan, 1906, Translated into English by Ann Schweir (1971). Manual of Political Economy, MacMillan London
De Micheli G (1994) Synthesis and optimization of digital circuits. McGraw-Hill Higher Education
Blythe SA, Walker RA (1999) Efficiently searching the optimal design space. In: GLS ’99: Proceedings of the Ninth Great Lakes Symposium on VLSI, p 192
Balakrishnan M, Marwedel P (1989) Integrated scheduling and binding: a synthesis approach for design space exploration. In: DAC ’89: Proceedings of the 26th ACM/IEEE Design automation conference, pp 68–74
Dutta R, Roy J, Vemuri R (1992) Distributed design-space exploration for high-level synthesis systems. In: DAC ’92: Proceedings of the 29th ACM/IEEE design automation conference. pp 644–650
Chaudhuri S, Blythe SA, Walker RA (1997) A solution methodology for exact design space exploration in a three-dimensional design space. IEEE Trans Very Large Scale Integr Syst 5(1):69–81
Wang G, Gong W, DeRenzi B, Kastner R (2007) Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization. ACM Trans. Design Autom. Electr Syst 12(4)
Kurra S, Singh NK, Panda PR (2007) The impact of loop unrolling on controller delay in high level synthesis. In: DATE ’07: Proceedings of the conference on Design, automation and test in Europe. pp 391–396
Dragomir O, Panainte E, Bertels K, Wong S (2008) Optimal unroll factor for reconfigurable architectures. In: Proceedings of ARC. pp 4–14
Gerlach J, Rosenstiel W (2000) A methodology and tool for automated transformational high-level design space exploration. In: ICCD. pp 545–548
Marwedel P, Landwehr B, Domer R (1997) Built-in chaining: introducing complex components into architectural synthesis. In: Proceedings of the ASP-DAC. pp 599–605
Corazao M, Khalaf M, Guerra L, Potkonjak M, Rabaey J (1996) Perfomance optimization using template mapping for datapath-intensive high-level synthesis.. IEEE Trans. Computer-Aided Design Integrated Circuits Syst 15(2):877–888
Xydis S, Skouroumounis C, Pekmestzi K, Soudris D, Economakos G (2010) Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. In: Proceedings of ISCAS
The ExPRESS group (2009) http://express.ece.ucsb.edu
Gupta S, Dutt N, Gupta R, Nicolau A (2002) Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Trans. Des. Autom. Electron. Syst 9:2004
C to Verilog, Circuit Design Automation, http://c-to-verilog.com/
point FFT source code, http://www.mit.edu/emin/source_code/fft/fft.c
Synopsys Inc. (2009) http://www.synopsys.com/products/
Artisan Components, TSMC 0.13 Library Databook
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer Science+Business Media B.V.
About this paper
Cite this paper
Xydis, S., Pekmestzi, K., Soudris, D., Economakos, G. (2011). A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_7
Download citation
DOI: https://doi.org/10.1007/978-94-007-1488-5_7
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-1487-8
Online ISBN: 978-94-007-1488-5
eBook Packages: EngineeringEngineering (R0)