Abstract
This chapter details the approaches that help to accelerate the receiver jitter tolerance testing thousandfold. According to the receiver characteristics and the test setup, we first propose a jitter tolerance extrapolation algorithm. Based on this algorithm, we then propose acceleration schemes for production test, as well as for characterization and silicon debugging. In this chapter, we first review the operation of a receiver in high-speed serial interfaces, and especially the clock data recovery block, under the influence of jitter, both in- and out-of-band. Then, we show how a jitter tolerance testing is conducted, including a detailed description of the jitter test signal generation. The key part is presented in a jitter extrapolation technique that will allow us to speed up the tests by inferring about the low BER performance from the actual tests undertaken at higher BER levels, in a fraction of time it would take otherwise.
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Fan, Y., Zilic, Z. (2011). Accelerating Receiver Jitter Tolerance Testing on ATE. In: Accelerating Test, Validation and Debug of High Speed Serial Interfaces. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9398-1_3
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DOI: https://doi.org/10.1007/978-90-481-9398-1_3
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