Abstract
As the technologies scale down into the nanometer range, the transistor leakage currents become a major concern. To overcome this problem, advanced control methods are mandatory, especially for circuits such as memories.
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Thomas, O., Belleville, M., Ferrant, R. (2010). SRAM Memory Cell Leakage Reduction Design Techniques in 65 nm Low Power PD-SOI CMOS. In: Amara, A., Ea, T., Belleville, M. (eds) Emerging Technologies and Circuits. Lecture Notes in Electrical Engineering, vol 66. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9379-0_10
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DOI: https://doi.org/10.1007/978-90-481-9379-0_10
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