Abstract
Circuit operation greatly depends on the ability to control and reproduce transistor and process parameters, such as oxide thickness, dielectric constants, doping levels, width and length. Variation in processing was in the past countered by defining process corners: boundaries in parameter variation that accounted for remaining process tolerances. With the improved control over processing, this batch-to-batch variation is largely under control.
However now a new class of phenomena has appeared: statistical variations. In conventional ICs, analog circuits with a differential operation (e.g. analog-to-digital converters) were already affected by this random parameter spread. The remaining variation between otherwise identical components is generally described by “mismatch” parameters. Next to these random phenomena also systematic errors called “offsets” play an increasingly important role Understanding and mitigating these effects requires statistical means and models.
The chapter will focus on the modeling of systematic and random effects that originate from physical, electrical, thermal and lithographical effects in devices causing intra-die variations.
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
The importance of this model extension is more in signaling a potential problem in the process than in accurately modeling a phenomenon.
- 2.
For ease of understanding only a uniformly distributed dopant is assumed, more complicated distributions must be numerically evaluated.
- 3.
The contribution of mobility reduction factor θ is next in line.
- 4.
Accuracy means that the standard deviation of a circuit parameter is within 10% of the prediction, see Sect. 15.4.7.
References
Sze, S.M.: Physics of Semiconductor Devices, 2nd edn. Wiley, New York (1981). (3rd edn. 2006, ISBN: 978-0-471-14323-9)
Brews, J.R.: MOSFET hand analysis using BSIM. IEEE Circuits Devices Mag. 28–36 (2006)
Enz, C.C., Krummenacher, F., Vittoz, E.A.: An analytical MOS transistor model valid in all regions of operations and dedicated to low-voltage and low-current applications. Analog Integr. Circuits Signal Process. J. 83–114 (1995)
Gildenblat, G., Xin, Li, Wu, W., Hailing, Wang, Jha, A., van Langevelde, R., Smit, G.D.J., Scholten, A.J., Klaassen, D.B.M.: PSP: An advanced surface-potential-based MOSFET model for circuit simulation. IEEE Trans. Electron Devices 1979–1993 (2006)
Gregor, R.W.: On the relationship between topography and transistor matching in an analog CMOS technology. IEEE Trans. Electron Devices 275–282 (1992)
Stathis, J.H., Zafar, S.: The negative bias temperature instability in MOS devices: A review. Microelectron. Reliab. 270–286 (2006)
Hook, T.B., Brown, J., Cottrell, P., Adler, E., Hoyniak, D., Johnson, J., Mann, R.: Lateral ion implant straggle and mask proximity effect. IEEE Trans. Electron Devices 1946–1951 (2003)
Drennan, P.G., Kniffin, M.L., Locascio, D.R.: Implications of proximity effects for analog design. In: IEEE Custom Integrated Circuits Conference 2006, pp. 169–176 (2006)
Bianchi, R.A., Bouche, G., Roux-dit-Buisson, O.: Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: Digest. International Electron Devices Meeting, pp. 117–120 (2002)
Su, K.-W., et al.: A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics. In: Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 245–248 (2003)
Wils, N., Tuinhout, H.P., Meijer, M.: Characterization of STI edge effects on CMOS variability. IEEE Trans. Semicond. Manuf. 59–65 (2009)
Ge, L., Adams, V., Loiko, K., Tekleab, D., Bo, X.-Z., Foisy, M., Kolagunta, V., Veeraraghavan, S.: Modeling and simulation of poly-space effects in uniaxially-strained etch stop layer stressors. In: IEEE International SOI Conference, pp. 25–26 (2007)
Tuinhout, H.P., Pelgrom, M.J.M., Penning de Vries, R., Vertregt, M.: Effects of metal coverage on MOSFET matching. In: Technical Digest International Electron Devices Meting, pp. 735–739 (1996)
Tuinhout, H.P., Bretveld, A., Peters, W.C.M.: Measuring the span of stress asymmetries on high-precision matched devices. In: International Conference on Microelectronic Test Structures, pp. 117–122 (2004)
Pelgrom, M.J.M., Vertregt, M., Tuinhout, H.P.: Matching of MOS Transistors. MEAD Course Material (1998–2009)
Mao-Feng et al.: Current mirror layout strategies for enhancing matching performance. Analog Integr. Circuits Signal Process. 28, 9–26 (2001)
McCreary, J.L.: Matching properties, and voltage and temperature dependence of MOS capacitors. IEEE J. Solid-State Circuits 608–616 (1981)
Shyu, J.-B., Temes, G.C., Yao, K.: Random errors in MOS capacitors. IEEE J. Solid-State Circuits 1070–1076 (1982)
Tuinhout, H.P., Elzinga, H., Brugman, J.T., Postma, F.: Accurate capacitor matching measurements using floating-gate test structures. In: IEEE International Conference on Microelectronic Test Structures, pp. 133–137 (1994)
Aparicio, R., Hajimiri, A.: Capacity limits and matching properties of integrated capacitors. IEEE J. Solid-State Circuits 384–393 (2002)
Drennan, P.G.: Diffused resistor mismatch modeling and characterization. In: Bipolar/BiCMOS Circuits and Technology Meeting, pp. 27–30 (1999)
Tuinhout, H.P., Hoogzaad, G., Vertregt, M., Roovers, R.L.J., Erdmann, C.: Design and characterisation of a high precision resistor ladder test structure. In: IEEE International Conference on Microelectronic Test Structures, pp. 223–228 (2002)
Lakshmikumar, K.R., Hadaway, R.A., Copeland, M.A.: Characterization and modeling of mismatch in MOS transistors for precision analog design. IEEE J. Solid-State Circuits 1057–1066 (1986)
Michael, C., Ismail, M.: Statistical modeling of device mismatch for analog MOS integrated circuits. IEEE J. Solid-State Circuits 154–166 (1992)
Forti, F., Wright, M.E.: Measurement of MOS current mismatch in the weak inversion region. IEEE J. Solid-State Circuits 138–142 (1994)
Croon, J.A., Sansen, W., Maes, H.E.: Matching Properties of Deep Sub-Micron MOS Transistors. Springer, Dordrecht (2005). ISBN 0-387-24314-3
Tuinhout, H.P.: Improving BiCMOS technologies using BJT parametric mismatch characterisation. In: Bipolar/BiCMOS Circuits and Technology Meeting, pp. 163–170 (2003)
Pelgrom, M.J.M., Duinmaijer, A.C.J., Welbers, A.P.G.: Matching properties of MOS transistors. IEEE J. Solid-State Circuits 1433–1440 (1989)
Brown, A.R., Roy, G., Asenov, A.: Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture. IEEE Trans. Electron Devices 3056–3063 (2007)
Mizuno, T., Okamura, J., Toriumi, A.: Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs. IEEE Trans. Electron Devices 2216–2221 (1994)
Pelgrom, M.J.M., Vertregt, M.: CMOS technology for mixed signal ICs. Solid-State Electron. 967–974 (1997)
Bastos, J., Steyaert, M., Roovers, R., Kinget, P., Sansen, W., Graindourze, B., Pergoot, A., Janssens, E.: Mismatch characterization of small size MOS transistors. In: Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 271–276 (1995)
Stolk, P.A., Widdershoven, F.P., Klaassen, D.B.M.: Modeling statistical dopant fluctuations in MOS transistors. IEEE Trans. Electron Devices 1960–1971 (1998)
Andricciola, P., Tuinhout, H.P.: The temperature dependence of mismatch in deep-submicrometer bulk MOSFETs. IEEE Electron Device Lett. 690–692 (2009)
Papoulis, A.: Probability, Random Variables, and Stochastic Processes, student edn. McGraw Hill, New York (1965). McGraw-Hill, 4th edn. (2001), ISBN 0-07-366011-6
Croon, J.A., Tuinhout, H.P., Difrenza, R., Knol, J., Moonen, A.J., Decoutere, S., Maes, H.E., Sansen, W.: A comparison of extraction techniques for threshold voltage mismatch. In: Proc. IEEE Int. Conf. on Microelectronic Test Structures, pp. 235–240 (2002)
Takeuchi, K., Hane, M.: Statistical compact model parameter extraction by direct fitting to variations. IEEE Trans. Electron Devices 1487–1493 (2008)
Cheng, B., Roy, S., Asenov, A.: Statistical compact model parameter extraction strategy for Intrinsic parameter fluctuation. In: Grasser, T., Selberherr, S. (eds.) Simulation on Semiconductor Processes and Devices, pp. 301–304. Springer, New York (2007)
Tuinhout, H.P.: Electrical characterisation of matched pairs for evaluation of integrated circuit technologies. Ph.D. Thesis, Delft University of Technology (2005). http://repository.tudelft.nl/file/82893/025295
Tuinhout, H.P., Vertregt, M.: Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures. IEEE Trans. Semicond. Manuf. 302–310 (2001)
Tuinhout, H.P., van Rossem, F., Wils, N.: High-precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system. In: IEEE International Conference on Microelectronic Test Structures, pp. 3–8 (2009)
Rey, W.J.J.: Introduction to Robust and Quasi-robust Statistical Methods. Springer, Berlin (1983). ISBN 0-387-12866-2
Pelgrom, M.J.M., v. Rens, A.C., Vertregt, M., Dijkstra, M.B.: A 25-Ms/s 8-bit CMOS A/D converter for embedded application. IEEE J. Solid-State Circuits 879–886 (1994)
Vertregt, M., Scholtens, P.C.S.: Assessment of the merits of CMOS technology scaling for analog circuit design. In: Proceedings ESSCIRC, pp. 57–64 (2004)
Pelgrom, M.J.M.: Low-power high-speed A/D conversion. In: ESSCIRC94, Low-power Workshop (1994)
Kinget, P., Steyaert, M.: Impact of transistor mismatch on the speed accuracy power trade-off. Custom Integrated Circuits Conference (1996)
Pelgrom, M.J.M., Tuinhout, H.P., Vertregt, M.: Transistor matching in analog CMOS applications. Invited Paper on International Electron Devices Meeting, pp. 915–918 (1998)
Doorn, T.S., ter Maten, E.J.W., Croon, J.A., Di Bucchianico, A., Wittich, O.: Importance sampling Monte Carlo simulations for accurate estimation of SRAM yield. In: European Solid-State Circuits Conference, pp. 230–233 (2008)
Acknowledgments
The authors are grateful for being able to use the insights and results of their colleagues at NXP Research. Without the useful discussions and critical comments this chapter would not exist.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Appendix: Derivation of Spatial Behavior
Appendix: Derivation of Spatial Behavior
The Fourier transform is used to analyze the behavior of spatially distributed functions. The spatial Fourier transform and its reverse form in two dimensions are defined as:
Inserting the geometry function as defined in Fig. 15.15:
As the x and y components are independent, the y component can be solved separately:
Using the trigonometric identity: cos (a+b)=cos (a)cos (b)−sin (a)sin (b). After some re-arrangement:
The variance of parameter ΔP between two rectangular devices is then found by substitution of (15.8) and the above-described models for the long and short correlation distance variations in (15.24). Mathematically the white noise model is described in the Fourier domain as a constant: \({\mathcal{P}}(\omega_{x},\omega_{y})={\mathcal{N}}\)
Considering that the ω x and ω y dimensions can be separated:
Using the standard integrals (CRC handbook 1984, p. 289 form 628 and 630):
the second integral is easy to solve, the first integral can be re-written into a series of squared sine waves, resulting in a π/2 if (a=L/2) represents the smaller of the two sine coefficients.
This is the first part of the equation. For solving the second part the gradient on the wafer must be modeled. A polar description would describe accurately the circular gradient. As this example only sensitivity parallel to the x axis is considered ω x =1/2W D where W D is the wafer diameter. Now ℘(ω x )=δ(1/2W D )
It will be clear that the delta function appears at a very low spatial frequency. For that low frequency, the (sin x/x) term can be considered to approach “1”. leaving:
Combining both results:
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media B.V.
About this chapter
Cite this chapter
Pelgrom, M., Tuinhout, H., Vertregt, M. (2010). Modeling of MOS Matching. In: Gildenblat, G. (eds) Compact Modeling. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-8614-3_15
Download citation
DOI: https://doi.org/10.1007/978-90-481-8614-3_15
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-8613-6
Online ISBN: 978-90-481-8614-3
eBook Packages: EngineeringEngineering (R0)