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Introduction

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Network-on-Chip Architectures

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 45))

Abstract

Since the beginning of the new millennium, the world of digital system design has witnessed an unprecedented phenomenon: a rapid and persistent reduction in feature sizes well into the nanoscale realm. Advancements in device technology and fabrication techniques have enabled designers to tread into previously unchartered territories; integration of billions of transistors on-die is now a reality. At such integration levels, it is imperative to employ parallelism to effectively utilize the transistors [1].

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Authors and Affiliations

  1. Department Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus

    Chrysostomos Nicopoulos

  2. Department Computer Science and Engineering, Pennsylvania State University, University Park, PA, USA

    Vijaykrishnan Narayanan & Chita R. Das

Authors
  1. Chrysostomos Nicopoulos
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  2. Vijaykrishnan Narayanan
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  3. Chita R. Das
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Correspondence to Chrysostomos Nicopoulos .

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Nicopoulos, C., Narayanan, V., Das, C.R. (2009). Introduction. In: Network-on-Chip Architectures. Lecture Notes in Electrical Engineering, vol 45. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3031-3_1

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  • DOI: https://doi.org/10.1007/978-90-481-3031-3_1

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-3030-6

  • Online ISBN: 978-90-481-3031-3

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