Digital RT Level Design: Flexibility to Save Energy

This chapter covers the final step of the proposed design flow: the design at register transfer level (RTL). Flexibility plays a central role in this design step, and is mainly discussed in this chapter. The proposed design is made ultraflexible such that it can, at all times, adapt optimally to its continuously changing user requirements and environments. In this context, it will be proven through various design examples that flexibility not only costs energy, but — on the contrary — also allows to save energy at run time. The innovative idea that flexibility and energy-efficiency do not have to be contradicting will be covered extensively in this chapter. Designing such a system, however, requires a whole new approach to now optimally balance power, performance, and flexibility. The main challenges are finding the optimal degree of flexibility and implementing this flexibility without an excessive power penalty.

In this chapter, a novel chip architecture, based on energy-efficient, nested, flexible modules (FLEXmodules) is introduced. These programmable modules enable a system, which can be clock and power gated, slowed down and reprogrammed with a very fine granularity. They make the system flexible and adaptive, while keeping its power consumption low.