Chapter

VLSI Systems and Computations

pp 327-336

VLSI Implementations of a Reduced Instruction Set Computer

  • Daniel T. FitzpatrickAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , Manolis G. H. KatevenisAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , David A. PattersonAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , Zvi PeshkessAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , Robert W. SherburneAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , John K. FoderaroAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , Howard A. LandmanAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , James B. PeekAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
  • , Carlo H. SéquinAffiliated withComputer Science Division/EECS Department, University of California at Berkeley
    • , Korbin S. Van DykeAffiliated withComputer Science Division/EECS Department, University of California at Berkeley

* Final gross prices may vary according to local VAT.

Get Access

Abstract

A general trend in computers today is to increase the complexity of architectures commensurate with the increasing potential of implementation technologies. Consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation[7]. The Reduced Instruction Set Computer (RISC) Project investigates a VLSI alternative to this trend. Our initial design is called RISC I.