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Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder

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Book cover Transactions on Computational Science XVII

Part of the book series: Lecture Notes in Computer Science ((TCOMPUTATSCIE,volume 7420))

Abstract

Reversible logic is playing a significant role in quantum computing as quantum operations are unitary in nature. Quantum computer performs computation at an atomic level; thereby doing high performance computations beyond the limits of the conventional computing systems. Reversible arithmetic units such as adders, subtractors, multipliers form the essential component of a quantum computing system. Among the adder designs, carry look-ahead is widely used in high performance computing due to its O (log n) depth. In this work, we present improved designs of both in-place and out-of-place reversible carry look-ahead adder proposed in [1]. The proposed designs utilize the properties of the reversible Peres gate and the TR gate to optimize the logic depth, quantum cost and gate count compared to the existing designs proposed in [1]. Both the improved designs assume no input carry (C0=0). While the first approach makes use of ancilla bits to store the sum outputs, the second approach stores the sum outputs in one of the input locations.

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References

  1. Draper, T.G., Kutin, S.A., Rains, E.M., Svore, K.M.: A logarithmic-depth quantum carry look-ahead adder. Quantum Information and Computation 6(4-5), 351–369 (2006)

    MathSciNet  MATH  Google Scholar 

  2. Landauer, R.: Irreversibility and Heat Generation in the Computing Process. IBM Journal of Research and Development 3, 183–191 (1961)

    Article  MathSciNet  Google Scholar 

  3. Bennett, C.H.: Logical Reversibility of Computation. IBM Journal of Research and Development, 525–532 (1973)

    Google Scholar 

  4. Shor, P.W.: Algorithms for Quantum Computation: Discrete Logarithms and Factoring. In: Proceeding of 35th Annual Symposium on Foundations of Computer science, pp. 124–134. IEEE Computer Society Press (November 1994)

    Google Scholar 

  5. Shor, P.W.: Polynomial-Time Algorithms for Prime Factorization and Discrete Logarithms on a Quantum Computer, vol. 2 (1997) quant-ph/9508027

    Google Scholar 

  6. Vedral, V., Bareno, A., Ekert, A.: Quantum networks for elementary arithmetic operations. Phys. Rev. A 54, 147–153 (1996)

    Article  MathSciNet  Google Scholar 

  7. Fredkin, E., Toffoli, T.: Conservative logic. International Journal of Theoretical Physics 21, 219–253 (1982)

    Article  MathSciNet  MATH  Google Scholar 

  8. Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, New York (2000)

    MATH  Google Scholar 

  9. Takahashi, Y., Kunihiro, N.: A linear-size quantum circuit for addition with no ancillary qubits. Quantum Information and Computation 5(6), 440–448 (2005)

    MathSciNet  MATH  Google Scholar 

  10. Takahashi, Y.: Quantum arithmetic circuits, a survey. Proceedings of IEICE Transactions E92-A(5), 1276–1283 (2009)

    Google Scholar 

  11. Peres, A.: Reversible logic and quantum computers. Phys. Rev. A, Gen. Phys. 32(6), 3266–3276 (1985)

    Article  MathSciNet  Google Scholar 

  12. Toffoli, T.: Reversible computing. Technical Report, MIT/LCS/TM-151, MIT Lab for Computer Science (1980)

    Google Scholar 

  13. Thapliyal, H., Ranganathan, N.: Design of Efficient Reversible Logic Based Binary and BCD Adder Circuits. To appear in ACM Journal of Emerging Technologies in Computing Systems (September 2012)

    Google Scholar 

  14. Smolin, J.A., DiVincenzo, D.P.: Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Physical Review A 53(4), 2855–2856 (1996)

    Article  MathSciNet  Google Scholar 

  15. Hung, W.N., Song, X., Yang, G., Yang, J., Perkowski, M.: Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Transactions on Computer-Aided Design 25(9), 1652–1663 (2006)

    Article  Google Scholar 

  16. Maslov, D., Miller, D.M.: Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT 3-qubit reversible circuits. IET Computers & Digital Techniques 1(2), 98–104 (2007)

    Article  Google Scholar 

  17. Draper, T.G.: Addition on a Quantum Computer, vol. 7 (2000) quant-ph/0008033

    Google Scholar 

  18. Trisetyarso, A., Meter, R.V.: Circuit design for a measurement-based quantum carry look-ahead adder. International Journal of Quantum Information 8(5), 843–867 (2010)

    Article  MATH  Google Scholar 

  19. Thapliyal, H., Arabnia, H.R.: Modified Carry Look-ahead BCD Adder with CMOS and Reversible Logic Implementation. In: Proceedings of CDES, pp. 64–69 (2006)

    Google Scholar 

  20. Thapliyal, H., Gupta, S.K.: Design of Novel Reversible Carry Look-ahead BCD Subtractor. In: 9th International Conference on Information Technology (ICIT 2006). IEEE (2006) 0-7695-2635-7/06 $20.00

    Google Scholar 

  21. DeBenedictis, E.: Reversible logic for supercomputing. In: 2nd Conference on Computing Frontiers, pp. 391–402 (2005)

    Google Scholar 

  22. Pai, Y., Chen, Y.: The Fastest Carry Look-ahead Adder. In: Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), pp. 434–436 (2004)

    Google Scholar 

  23. Kaye, P.: Reversible addition circuit using one ancillary bit with application to quantum computing, vol.2 (2004) quanth-ph/ 0408173

    Google Scholar 

  24. Takahashi, Y., Kunihiro, N.: A fast quantum circuit for addition with few qubits. Quantum Information and computation 8(6-7), 636–649 (2008)

    MathSciNet  MATH  Google Scholar 

  25. Mohammadi, M., Haghparast, M., Eshghi, M., Navi, K.: Minimization optimization of Reversible BCD-full adder/subtractor using genetic algorithm and don’t care concept. International Journal of Quantum Information 7(5), 969–989 (2009)

    Article  MATH  Google Scholar 

  26. Thapliyal, H., Arabnia, H.R., Srinivas, M.B.: Efficient Reversible Logic Design of BCD Subtractors. In: Gavrilova, M.L., Tan, C.J.K. (eds.) Transactions on Computational Science III. LNCS, vol. 5300, pp. 99–121. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  27. Thapliyal, H., Arabnia, H.R., Srinivas, M.B.: Reduced Area Low Power High Throughput BCD Adders. In: Proceedings of the 11th International CSI Computer Conference, vol. 2, pp. 59–64 (2006)

    Google Scholar 

  28. Thapliyal, H., Arabnia, H.R., Bajpai, R., Sharma, K.K.: Partial Reversible Gates (PRG) for Reversible BCD Arithmetic. In: Proceedings of 2007 International Conference on Computer Design (CDES 2007), USA, pp. 97–98 (2007) ISBN 1-60132-036-1

    Google Scholar 

  29. Thapliyal, H., Arabnia, H.R., Bajpai, R., Sharma, K.K.: Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs. In: Proceedings of International Conference on Parallel & Distributed Processing Techniques & Applications (PDPTA 2007), USA, pp. 449–450 (2007) ISBN 1-60132-022-1

    Google Scholar 

  30. Thapliyal, H., Vinod, A.P., Arabnia, H.R.: Combined Integer and Floating Point Multiplication Architecture (CIFM) for FPGAs and its Reversible Logic Implementation. In: 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2006), San Juan, Puerto Rico, pp. 148–154 (2006)

    Google Scholar 

  31. Thapliyal, H., Verma, V., Arabnia, H.R.: A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. In: Proceedings of the 2006 International Conference on Computer Design and Conference on Computing in Nanotechnology (CDES 2006), Las Vegas, USA, pp. 36–38 (June 2006) ISBN 1-60132-009-4

    Google Scholar 

  32. Thapliyal, H., Arabnia, H.R.: Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. In: Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology (CDES 2006), Las Vegas, USA, pp. 70–74 (June 2006) ISBN 1-60132-009-4

    Google Scholar 

  33. Thapliyal, H., Arabnia, H.R.: Modified Carry Look-ahead BCD Adder with CMOS and Reversible Logic Implementation. In: Proceedings of the 2006 International Conference on Computer Design and Conference on Computing in Nanotechnology (CDES 2006), Las Vegas, USA, pp. 64–69 (June 2006) ISBN 1-60132-009-4

    Google Scholar 

  34. Thapliyal, H., Rameshwar, A., Bajpai, R., Arabnia, H.R.: Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. In: Proceedings of the 2006 International Conference on Computer Design and Conference on Computing in Nanotechnology (CDES 2006), Las Vegas, USA, pp. 130–132 (June 2006) ISBN 1-60132-009-4

    Google Scholar 

  35. Gopineedi, P., Thapliyal, H., Srinivas, M.B., Arabnia, H.R.: Novel and Efficient 4:2 and 5:2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations. In: Proceedings of the 2006 International Conference on Embedded Systems and Applications, ESA 2006, Las Vegas, USA, pp. 160–166 (June 2006) ISBN 1-60132-017-5

    Google Scholar 

  36. Thapliyal, H., Ranganathan, N.: Design of reversible sequential circuits optimizing quantum costs, delay, and garbage outputs. ACM Journal on Emerging Technologies in Computer Systems 6(4), Article 14 (2010)

    Google Scholar 

  37. Cuccaro, S.A., Draper, T.G., Kutin, S.A., Moulton, D.: A new quantum ripple-carry addition circuit (2004), http://arXiv.org/quant-ph/0410184

  38. Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out (2009), http://arxiv.org/abs/0910.2530

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Author information

Authors and Affiliations

  1. Department of Computer Science and Engineering, University of South Florida, USA

    Himanshu Thapliyal

  2. Department of E &C, PES Institute of Technology, India

    H. V. Jayashree & A. N. Nagamani

  3. Department of Computer Science, The University of Georgia, USA

    Hamid R. Arabnia

Authors
  1. Himanshu Thapliyal
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  2. H. V. Jayashree
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  3. A. N. Nagamani
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  4. Hamid R. Arabnia
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Editors and Affiliations

  1. Department of Computer Science, University of Calgary, 2500 University Drive N.W., T2N 1N4, Calgary, AB, Canada

    Marina L. Gavrilova

  2. Exascala Ltd., Unit 9, 97 Rickman Drive, B15 2AL, Birmingham, UK

    C. J. Kenneth Tan

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Thapliyal, H., Jayashree, H.V., Nagamani, A.N., Arabnia, H.R. (2013). Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. In: Gavrilova, M.L., Tan, C.J.K. (eds) Transactions on Computational Science XVII. Lecture Notes in Computer Science, vol 7420. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-35840-1_4

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  • DOI: https://doi.org/10.1007/978-3-642-35840-1_4

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-35839-5

  • Online ISBN: 978-3-642-35840-1

  • eBook Packages: Computer ScienceComputer Science (R0)

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