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Spectroscopic Ellipsometry for Inline Process Control in the Semiconductor Industry

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Ellipsometry at the Nanoscale

Abstract

Building high-performance silicon CMOS or III/V devices requires many structural process steps, where a physical layer (dielectric, epitaxial semiconductor, gate electrode, or metal contact) is first deposited across the wafer and then partially removed by a masked or blanket etch process. Whenever possible, the deposition and etch processes are verified by a thickness metrology step. Typically, a latest-generation CMOS process flow contains about 100 thickness measurements, at least during the development of the technology. The metrology method of choice in the semiconductor industry is spectroscopic ellipsometry, because it is fast, non-destructive, and capable of measuring product wafers in small areas (30–50 \(\upmu {}\)m beam diameter) set aside in the scribe grid. This chapter will describe several typical applications of ellipsometry in CMOS and III/V device manufacturing and address capabilities and limitations and how future basic research on optical properties of materials can benefit the industry.

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Notes

  1. 1.

    The node length is the dynamical random access memoriy (DRAM) half pitch of transistors for the technology.

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Acknowledgments

This work was carried out over a ten-year period at Motorola (and later Freescale, GlobalFoundries, IBM, and New Mexico State University). The author acknowledges contributions from Mariam Sadaka, Bich-Yen Nguyen, Jamie Schaeffer, Dina Triyoso, Mark Raymond, and many others. The work at New Mexico State University was partially supported by the National Science Foundation (DMR-1104934).

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Correspondence to Stefan Zollner .

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Zollner, S. (2013). Spectroscopic Ellipsometry for Inline Process Control in the Semiconductor Industry. In: Losurdo, M., Hingerl, K. (eds) Ellipsometry at the Nanoscale. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33956-1_18

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  • DOI: https://doi.org/10.1007/978-3-642-33956-1_18

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