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Verifying a Logic Design

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Logic Circuit Design

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Abstract

The problem considered in this chapter is this: Having designed an asynchronous circuit according to a given word-recognition tree, or flow table, we next want to verify our logic design by developing a minimal length events graph with which to completely test the circuit’s input–output behaviour. In the literature, this is usually referred to as functional testing. In general, the problem is seen as unsolvable. Mead and Conway (1980) put it this way: ‘Complete functional testing of complex systems with internal sequencing is not possible in general, and most integrated system chips manufactured, even at 1978 levels of complexity, are not economically testable for even a small fraction of their possible internal states.’

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  1. Bärenkogelweg 21, 2371, Hinterbrühl, Austria

    Shimon P. Vingron

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  1. Shimon P. Vingron
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Vingron, S.P. (2012). Verifying a Logic Design. In: Logic Circuit Design. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27657-6_18

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  • DOI: https://doi.org/10.1007/978-3-642-27657-6_18

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