Abstract
In this article, we describe current state-of-the art processor designs, the design challenges faced by technology, and design scaling slow-down, problems with the new design paradigms and potential solutions as well as longer-term trends and requirements for future processors and systems. With technology and design scaling slowing down, the processor industry rapidly moved from high-frequency designs to multi-core chips in order to keep delivering the traditionally expected performance improvements. However, this rapid paradigm change created a whole new set of problems for the efficient usage of these multi-core designs in large-scale systems. Systems need to satisfy an increasing demand in throughput computing while at the same time still growing single-thread performance significantly. The increase in processor cores poses severe challenges to operating system and application development in order to exploit the available parallelism. It also requires new programming models (e.g. OpenCL*). Furthermore, commercial server systems are more and more enriched with special-purpose processors because these specialty engines are able to deliver more performance within the same power envelope than general-purpose microprocessors for certain applications. We are convinced that future processors and systems need to be designed with tight collaboration between the hardware and software community to ensure the best possible exploitation of physical resources. In the post-exponential growth era, hardware designs need to heavily invest in programmability features in addition to the traditional performance improvements.
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References
Davenport, T.H., Harris, J.G.: Competing on Analytics: the New Science of Winning. Harvard Business School, Boston (2007)
Hazucha, P., Karnik, T., Maiz, J., Walstra, S., Bloechel, B., Tschanz, J., Dermer, G., Hareland, S., Armstrong, P., Borkar, S.: Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-μm to 90-nm generation. IEEE IEDM (International Electron Devices Meeting) 2003, Technical Digest, pp. 523–526 (2003). doi: 10.1109/IEDM.2003.1269336
Haque, I.S., Pande, V.S.: GPUs: TeraFLOPS or TeraFLAWED? www.cs.stanford.edu/people/ihaque/posters/sc-2009.pdf. Accessed 20 Sept 2010
Meaney, P., Swaney, S., Sanda, P., Spainhower, L.: IBM z990 soft error detection and recovery. IEEE Transactions on device and materials reliability, Vol. 5, No. 3, September 2005, pg. 419–427
Mitran, M., Sham, I., Stepanian, L.: Decimal floating-point in Java 6: best practices. www-304.ibm.com/partnerworld/wps/servlet/ContentHandler/whitepaper/power/java6_sdk/best_practice. Accessed Jan 2009
Pleiter D.: QPACE: QCD Parallel Computing on the Cell. www.itwm.fhg.de/hpc/workshop/mic/Qpace_%28Dirk_Pleiter_-_Desy%29.pdf. Accessed 28 Oct 2008
www.top500.org.Accessed 29 Sept2010
www.top500.org/overtime/list/35/procarch. Accessed 29 Sept 2010
www.top500.org/lists/2010/06/performance_development. Accessed 29 Sept 2010
https://asc.llnl.gov/publications/leadingHPC.pdf. Accessed 29 Sept 2010
https://asc.llnl.gov/computing_resources/sequoia/index.html. Accessed 29 Sept 2010
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© 2011 Springer-Verlag Berlin Heidelberg
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Roth, P.H., Jacobi, C., Weber, K. (2011). Superprocessors and Supercomputers. In: Hoefflinger, B. (eds) Chips 2020. The Frontiers Collection. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23096-7_10
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DOI: https://doi.org/10.1007/978-3-642-23096-7_10
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