Abstract
In the paper the CAD system dedicated for modeling, verification, and synthesis of concurrent controllers modeled by interpreted Petri net is presented. Petri net model can be prepared as graph or as textual form. Controllers specified by Petri nets can be analyzed and implemented using method suitable for such model. For verification of Petri net another part of system is used. Moreover, the results of verification are decomposition of net into several communicating state machines (as finite state machines, FSMs). After verification it is possible to transform Petri net model into HDLs model (VHDL and Verilog) and alternatively into EDIF or XNF netlist format. Such prepared models are also simulated and synthesized using other academic or commercial CAD systems. The system has been developing at University of Zielona Góra. Development of new methods of modeling, verification and synthesis has been contributed to make an attempt the new integrated version of the system. In addition, using of Java environment gives opportunity to work out the system that is platform independent.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Adamski, M.: Parallel Controller Implementation using Standard PLD Software. In: Moore, W.R., Luk, W. (eds.) FPGAs, Abingdon EE & CS, England, pp. 296–304 (1991)
Adamski, M., Węgrzyn, M.: Design of Reconfigurable Logic Controllers from Petri Net-based specifications. In: The 4th IFAC Workshop on Discrete-Event System Design, DESDes 2009, Gandia, pp. 233–238 (2009)
Adamski, M., Karatkevich, A., Wegrzyn, M. (eds.): Design of Embedded Control Systems. Springer, New York (2005)
Adamski, M., Węgrzyn, M., Wolański, P.: Simulating and synthesising of reconfigurable logic controllers using VHDL. In: Proc. of the 42 IWK, Ilmenau, Germany, vol. 1, pp. 522–527 (1997)
Biliński, K.: Application of Petri Nets in parallel controllers design. Ph.D. Thesis, University of Bristol, Electrical and Electronic Engineering Department (1996)
Chmielewski, S., Węgrzyn, M.: Modelling and synthesis of automata in HDLs. In: Romaniuk, R.S. (ed.) Proceedings of SPIE, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, vol. 6347 (2006); 63470J1-13
David, R., Alla, H.: Petri Nets and Grafcet. Prentice Hall, New York (1992)
International Electrotechnical Commission, International standard IEC 61131-3, Programmable Controllers, Part 3: Programming Languages (1992)
Mathony, H.J.: Universal logic design algorithm and its application the synthesis of two-level switching circuits. IEE Proceedings, Pt.E - Computers and Digital Techniques 136(3), 171–177 (1989)
Minns, P., Elliott, I.: FSM based Digital Design using Verilog HDL. John Wiley & Sons, Ltd., Chichester (2008)
Murata, T.: Petri Nets: Properties, Analysis and Applications. Proceedings of the IEEE 77(4), 541–580 (1989)
Pardey, J., Bolton, M.: Logic Synthesis of Synchronous Parallel Controllers. In: Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, pp. 454–457 (1991)
Węgrzyn, A.: Symbolic Analysis of Logical Control Devices using Selected Methods of Petri Net Analysis. Ph.D. Thesis, Warsaw University of Technology (2003) (in Polish)
Węgrzyn, A., Jóźwiak, I.: Visualization of control process by means of Petri nets and database. In: Romaniuk, R.S. (ed.) Proceedings of SPIE, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, vol. 6347 (2006); 63472Q1-8
Węgrzyn, A., Węgrzyn, M.: PeNCAD System - From Modeling to Synthesis of Concurrent Controllers. In: The 5th IEEE East-West Design & Test International Symposium, Yerevan, pp. 384–389 (2007)
Węgrzyn, A., Węgrzyn, M.: On Textual Specification of Petri Nets for Control Algorithms. In: The 5th IEEE East-West Design & Test International Symposium, Yerevan, pp. 603–607 (2007)
Węgrzyn, M.: Hierarchical implementation of Logic controllers by means of Petri nets and FPGAs. Ph.D. Thesis, Warsaw University of Technology (1998) (in Polish)
Węgrzyn, M.: Implementation of Safety Critical Logic Controller by means of FPGA. Annual Reviews in Control 27, 55–61 (2003)
Węgrzyn, M.: Petri Net Decomposition Approach for Partial Reconfiguration of Logic Controllers. In: Adamski, M., Gomes, L., Węgrzyn, M., Łabiak, G. (eds.) Discrete-Event System Design 2006, A Proceedings volume from the IFAC Workshop, DESDes 2006, pp. 323–328. University of Zielona Góra Press, Rydzyna (2006)
Węgrzyn, M., Adamski, M., Monteiro, J.L.: The Application of Reconfigurable Logic to Controller Design. Control Engineering Practice 6, 879–887 (1998)
Węgrzyn, M., Węgrzyn, A.: Implementation of Concurrent Logic Controllers based on Decomposition into State Machine Components. Radio-Electronics and Informatics 3, 44–47 (2006)
Wolański, P.: VHDL Register Transfer Level modeling of digital systems by means of Petri nets. Ph.D. Thesis, Warsaw University of Technology (1998) (in Polish)
Xilinx Inc. (2010), http://www.xilinx.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Węgrzyn, M., Węgrzyn, A. (2011). 9 PeNLogic – System for Concurrent Logic Controllers Design. In: Adamski, M., Barkalov, A., Węgrzyn, M. (eds) Design of Digital Systems and Devices. Lecture Notes in Electrical Engineering, vol 79. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17545-9_9
Download citation
DOI: https://doi.org/10.1007/978-3-642-17545-9_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17544-2
Online ISBN: 978-3-642-17545-9
eBook Packages: EngineeringEngineering (R0)