Skip to main content
SpringerLink
Log in
Book cover

Digitale Hardware/Software-Systeme pp 155–233Cite as

Eigenschaftsprüfung

  • Chapter
  • First Online:

  • 4947 Accesses

Part of the book series: eXamen.press ((EXAMEN,volume 0))

Zusammenfassung

Ziel der Eigenschaftsprüfung ist es, zu testen, ob die Implementierung funktionale und nichtfunktionale Anforderungen erfüllt (siehe Abb. 5.1). Bei der Prüfung funktionaler Eigenschaften wird das Strukturmodell der Implementierung dahin gehend überprüft, ob dieses alle funktionalen Anforderungen erfüllt. Dabei werden typischerweise Gefahrlosigkeits- und Lebendigkeitseigenschaften geprüft. Eine Gefahrlosigkeitseigenschaft besagt, dass nie etwas Schlimmes passieren wird, während eine Lebendigkeitseigenschaft besagt, dass immer irgendwann etwas Gutes passieren wird.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   39.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

  1. Ghamarian, A. H., M. C. W. Geilen, S. Stuijk, T. Basten, A. J. M. Moonen, M. J. G. Bekooij, B. D. Theelen und M. R. Mousavi: Throughput Analysis of Synchronous Data Flow Graphs. In: Proceedings of the International Conference on Application of Concurrency to System Design (ACSD), Seiten 25–36, 2006.

    Google Scholar 

  2. Emerson, E. A. und R. J. Trefler: Parametric Quantitative Temporal Reasoning. In: Proceedings of the Symposium on Logic in Computer Science (LICS), Seiten 336–343, 1999.

    Google Scholar 

  3. Fettweis, A.: Realizability of Digital Filter Networks. Archiv Elek. übertragung, 30(2):90–96, 1976.

    Google Scholar 

  4. Cassandras, C. G. und S. Lafortune: Introduction to Discrete Event Systems. Springer, New York, NY, U.S.A., 1999.

    MATH  Google Scholar 

  5. Dill, D. L.: Timing Assumptions and Verification of Finite-State Concurrent Systems. In: Proceedings of the International Workshop on Automatic Verification Methods for Finite State Systems, Seiten 197–212, 1990.

    Google Scholar 

  6. Govindarajan, R. und G. R. Gao: Rate-Optimal Schedule for Multi-Rate DSP Computations. Journal of VLSI Signal Processing Systems, 9(3):211–232, 1995.

    Article  Google Scholar 

  7. Wolper, P., M. Y. Vardi und A. P. Sistla: Reasoning about Infinite Computation Paths. In: Proceedings of the Symposium on Foundations of Computer Science, Seiten 185–194, 1983.

    Google Scholar 

  8. Biere, A., A. Cimatti, E. M. Clarke und Y. Zhu: Symbolic Model Checking without BDDs. In: Tools and Algorithms for Construction and Analysis of Systems, Seiten 193–207. Springer, Berlin, Heidelberg, 1999.

    Google Scholar 

  9. Markey, N. und P. Schnoebelen: Symbolic Model Checking of Simply-Timed Systems. In: Proceedings of the International Conference on Formal Modeling and Analysis of Timed Systmes (FORMATS), Seiten 102–117, 2004.

    Google Scholar 

  10. Lichtenstein, O. und A. Pnueli: Checking that Finite State Concurrent Programs Satisfy their Linear Specification. In: Proceedings of the Symposium on Principles of Programming Languages (POPL), Seiten 97–107, 1985.

    Google Scholar 

  11. Clarke, E. M. und E. A. Emerson: Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic. In: Processings of the Workshop on Logic of Programs, Seiten 52–71, 1982.

    Google Scholar 

  12. Alur, R.: Timed Automata. In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 8–22, 1999.

    Google Scholar 

  13. Laroussinie, F., P. Schnoebelen, und M. Turuani: On the Expressivity and Complexity of Quantitative Branching-Time Temporal Logics. In: Proceedings of the Latin American Symposium on Theoretical Informatics (LATIN), Seiten 437–446, 2000.

    Google Scholar 

  14. Yuan, J., C. Pixley und A. Aziz: Constrained-Based Verification. Springer, New York, NY, U.S.A., 2006.

    Google Scholar 

  15. Ghamarian, A. H.: Timing Analysis of Synchronous Data Flow Graphs. Doktorarbeit, Eindhoven University of Technology, The Netherlands, 2008.

    Google Scholar 

  16. Clarke, E. M., E. A. Emerson und A. P. Sistla: Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications. ACM Transactions on Programming Languages and Systems (TOPLAS), 8(2):244–263, 1986.

    Article  MATH  Google Scholar 

  17. Alur, R., C. Courcoubetis und D. L. Dill: Model Checking in Dense Real-Time. Information and Computation, 104(1):2–34, 1993.

    Article  MATH  MathSciNet  Google Scholar 

  18. Reiter, R.: Scheduling Parallel Computations. Journal of the ACM, 15(4):590–599, 1968.

    Article  MATH  Google Scholar 

  19. Hopcroft, J. E., R. Motwani und J. D. Ullman: Einführung in die Automatentheorie, Formale Sprachen und Komplexitätstheorie. Pearson Studium, Deutschland, München, 2002. 2. Auflage.

    Google Scholar 

  20. Girault, C. und R. Valk: Petri Nets for Systems Engineering – A Guide to Modeling, Verification, and Application. Springer, Berlin, Heidelberg, New York, 2003.

    Google Scholar 

  21. Biere, A., A. Cimatti, E. M. Clarke, M. Fujita und Y. Zhu: Symbolic Model Checking Using SAT Procedures instead of BDDs. In: Proceedings of the Design Automation Conference (DAC), Seiten 317–320, 1999.

    Google Scholar 

  22. Queille, J.-P. und J. Sifakis: Specification and Verification of Concurrent Systems in CESAR. In: Proceedings of the Symposium on Programming, Seiten 337–351, 1982.

    Google Scholar 

  23. Godefroid, P.: Partial-Order Methods for the Verification of Concurrent Systems: An Approach to the State-Explosion Problem. Springer, New York, NY, U.S.A., 1996.

    Google Scholar 

  24. Baccelli, F., G. Cohen, G. J. Olsder und J.-P. Quadrat: Synchronization and Linearity: An Algebra for Discrete Event Systems. John Wiley & Sons, Inc., Chichester, West Sussex, England, 1992.

    MATH  Google Scholar 

  25. Cochet-Terrasson, J., G. Cohen, S. Gaubert, M. Mc Gettrick und J.-P. Quadrat: Numerical Computation of Spectral Elements in Max-Plus Algebra. In: Proceedings of the Conference on System Structure and Control, Seiten 667–674, 1998.

    Google Scholar 

  26. Wang, C., G. D. Hachtel und F. Somenzi: Abstraction Refinement for Large Scale Model Checking. Springer, New York, NY, U.S.A., 2006.

    Google Scholar 

  27. Gerth, R., D. Peled, M. Y. Vardi und P. Wolper: Simple On-the-Fly Automatic Verification of Linear Temporal Logic. In: Proceedings of the International Symposium on Protocol Specification, Testing and Verification, Seiten 3–18, 1996.

    Google Scholar 

  28. Ghamarian, A. H., S. Stuijk, T. Basten, M. C. W. Geilen und B. D. Theelen: Latency Minimization for Synchronous Data Flow Graphs. In: Proceedings of the Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD), Seiten 189–196, 2007.

    Google Scholar 

  29. Emerson, E. A., A. K. Mok, A. P. Sistla und J. Srinivasan: Quantitative Temporal Reasoning. In: Proceedings of the International Conference on Computer Aided Verification (CAV), Seiten 136–145, 1990.

    Google Scholar 

  30. Kropf, Thomas: Introduction to Formal Hardware Verification. Springer, Berlin, Heidelberg, 1999.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Lehrstuhl Hardware-Software-Co-Design, Universität Erlangen-Nürnberg, Am Weichselgarten 3, 91058, Erlangen, Deutschland

    Christian Haubelt & Jürgen Teich

Authors
  1. Christian Haubelt
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Jürgen Teich
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Christian Haubelt .

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Haubelt, C., Teich, J. (2010). Eigenschaftsprüfung. In: Digitale Hardware/Software-Systeme. eXamen.press, vol 0. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-05356-6_5

Download citation

Publish with us

Policies and ethics

Search

Navigation