Hardware for Neural Networks

Abstract

The simulation of neural networks on conventional computers is time-consuming because parallel structures and processes are transferred to a sequential machine. New computational means oriented to the realization of neural network paradigms were developed, these are called neurocomputers. Universal and specialized neurocomputers [1–7] were created. In this chapter, several versions of hardware for the proposed neural networks will be considered. The purpose of creating the neurocomputer was to increase the speed and expansion of simulated neural networks. At the Institute of Cybernetics of the National Academy of Sciences, Ukraine, under the management of the Doctor of Sciences E. M. Kussul, the first neurocomputer for associative-projective neural networks was developed and tested. The block diagram of the neurocomputer, named NIC, is given in Fig. 7.1. The model consists of two basic blocks: the block of processing modules and the control unit. The former contains the random access memory (RAM), arithmetic-logical unit (ALU), multiplexer (MUX₁), shift register (SRG₁) and unit of binary counters (St₁). The latter contains the high-speed memory unit (CM), arithmetic-logical unit (ALU₂), shift registers (SRG₂ and SRG₃), multiplexer (MUX₂), binary counter (Ct₂), training address register (IRG), and synchronizing circuit (not shown in the figure).