Into the Nano Era

Volume 106 of the series Springer Series in Materials Science pp 191-223

Transistor Scaling to the Limit

  • T. -J. K. LiuAffiliated with
  • , L. ChangAffiliated withDesign and Technology Solutions, IBM T.J. Watson Research Center

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The steady miniaturization of the metal-oxide-semiconductor field-effect transistor (MOSFET) with each new generation of complementary-MOS (CMOS) technology has yielded continual improvements in integrated-circuit performance and cost per function for more than 40 years. Until recently, transistor scaling generally followed simple rules [1] with slight modification (Table 8.1) [2, 3] to provide for improvements in circuit speed and density with reduction in power consumption per function, while maintaining reliability and electrostatic integrity (gate voltage control of the source-to-channel potential barrier) of the device itself. As a result, MOSFET scaling was able to progress at an exponential rate [4], yielding commensurate improvements in integration, cost, and performance, with revolutionary impact to usher in the Information Age.