Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Volume 4644 of the series Lecture Notes in Computer Science pp 566-575

Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers

  • Henrik ErikssonAffiliated withSP Technical Research Institute of Sweden, Box 857, SE-501 15 Borås

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An evaluation of the fault tolerance which can be achieved by the use of time-redundancy techniques in integer multipliers has been conducted. The evaluated techniques are: swapped inputs, inverted reduction tree, a novel use of the half precision mode in a twin-precision multiplier, and a combination of the first two techniques. The faults which have been injected are single stuck-at-zero or stuck-at-one faults. Error detection coverage has been the evaluation criteria. Depending on the technique, the attained error detection coverage spans from 25% to 90%.