Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers

  • Henrik Eriksson
Conference paper

DOI: 10.1007/978-3-540-74442-9_55

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4644)
Cite this paper as:
Eriksson H. (2007) Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers. In: Azémard N., Svensson L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg

Abstract

An evaluation of the fault tolerance which can be achieved by the use of time-redundancy techniques in integer multipliers has been conducted. The evaluated techniques are: swapped inputs, inverted reduction tree, a novel use of the half precision mode in a twin-precision multiplier, and a combination of the first two techniques. The faults which have been injected are single stuck-at-zero or stuck-at-one faults. Error detection coverage has been the evaluation criteria. Depending on the technique, the attained error detection coverage spans from 25% to 90%.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2007

Authors and Affiliations

  • Henrik Eriksson
    • 1
  1. 1.SP Technical Research Institute of Sweden, Box 857, SE-501 15 BoråsSweden

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