The Berkeley View: A New Framework and a New Platform for Parallel Research

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Abstract

The recent switch to parallel microprocessors is a milestone in history of computing. Industry has laid out a roadmap for multicore designs that preserve the programming paradigm of the past via binary-compatibility and cache-coherence. Conventional wisdom is now to double the number of cores on a chip with each silicon generation. A multidisciplinary group of Berkeley researchers met for 18 months to discuss this change. Our investigations into the future opportunities in led to the follow recommendations which are more revolutionary what industry plans to do:

  • The target should be 1000s of cores per chip, as this hardware is the most efficient in MIPS per watt, MIPS per area of silicon, and MIPS per development dollar.

  • To maximize application efficiency, programming models should support a wide range of data types and successful models of parallelism: data-level parallelism, independent task parallelism, and instructionlevel parallelism.

  • Should play a larger role than conventional compilers in translating parallel programs.

The conventional path to architecture innovation is to study a benchmark suite like SPEC or Splash to guide and evaluate innovation. A problem for innovation in parallelism iit best. Hence, it seems unwise to let a set of old programs from the past drive an investigation into parallel computing of the future.