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A Prefetching Algorithm for Multi-speed Disks

  • Conference paper
Book cover Transactions on High-Performance Embedded Architectures and Compilers I

Part of the book series: Lecture Notes in Computer Science ((THIPEAC,volume 4050))

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Abstract

Power consumption of disk based storage systems is becoming an increasingly pressing issue for both the commercial and the scientific application domains. Prior work proposed several hardware based approaches to reducing disk power consumption by making use of techniques such as spinning down idle disks and rotating them at lower speeds than the maximum speed possible. While such techniques are certainly very important, it is also critical to consider the influence the software can exercise in shaping the power consumption of disk-intensive application programs. Motivated by this observation, the main goal of this work is to study whether an optimizing compiler can be used for increasing the power benefits that could be obtained from multi-speed disks. Specifically, we propose and experimentally evaluate a compiler-directed energy-aware data prefetching scheme for scientific applications that process disk-resident data sets. This scheme automatically determines the prefetch distances for all disk access instructions, the disk speeds to be employed, and the associated disk layouts (striping parameters) in a unified setting. We implemented the proposed approach within an optimizing compiler framework and conducted experiments with several disk-intensive applications. Our experimental evaluation shows that the proposed approach brings significant reductions in disk energy consumption over a state-of-the-art software-based I/O prefetching mechanism that does not take into account energy consumption explicitly. Our results also show that the energy-aware prefetching scheme does not bring any extra performance penalties and the energy reductions achieved are consistent across a wide spectrum of values of the simulation parameters. We also show that our scheme can be extended to multiple application scenarios using a hierarchical disk layout determination.

This work is supported in part by NSF grants #0444158 and #0406340, and a grant from the GSRC. This paper extends the Computing Frontiers 2006 paper ?, by explaining how our approach can be extended to handle multiple application scenario and evaluating it.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA 16802, USA

    Seung Woo Son & Mahmut Kandemir

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  1. Seung Woo Son
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  2. Mahmut Kandemir
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Editors and Affiliations

  1. Department of Computer Science and Engineering, Chalmers University of Technology, 412 96, Gothenburg, Sweden

    Per Stenström

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Son, S.W., Kandemir, M. (2007). A Prefetching Algorithm for Multi-speed Disks. In: Stenström, P. (eds) Transactions on High-Performance Embedded Architectures and Compilers I. Lecture Notes in Computer Science, vol 4050. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-71528-3_20

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  • DOI: https://doi.org/10.1007/978-3-540-71528-3_20

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-71527-6

  • Online ISBN: 978-3-540-71528-3

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