Skip to main content

Synthesis of control units with field-programmable logic devices

  • Chapter
  • 446 Accesses

Part of the book series: Lecture Notes Electrical Engineering ((LNEE,volume 22))

Abstract

The chapter discusses contemporary field-programmable logic devices and their evolution, starting from the simplest programmable logic devices, such as PLA, PAL, GAL and PROM, and finishing with very sophisticated chips such as CPLD and FPGA. This analysis shows particular features of different elements and permits to optimize the control unit logic circuits, in which some particular elements are used. The CMCU has some features of both FSM and MCU. Therefore main design and optimization methods applied in case of these two types of control units are presented in the main part of the chapter.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD   169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1. http://www.altera.com.

    Google Scholar 

  2. 2. http://www.atmel.com.

    Google Scholar 

  3. 3. http://www.xilinx.com.

    Google Scholar 

  4. A. A.Barkalov and A. Bucowiec. Synthesis of mealy finite-states machines for interpretation of verticalized flow-charts. Theoretical and applied informatics, 39–51, 2005.

    Google Scholar 

  5. M. Adamski and A. Barkalov. Architectural and Sequential Synthesis of Digital Devices. University of Zielona Góra Press, 2006.

    Google Scholar 

  6. Microprogram optimization: a survey. IEEE Transactions of Computers, (10):962–973, 1976.

    Google Scholar 

  7. A. Agrawala and T. Rauscher. Foundations of Microprogramming. Academic Press, New York, 1976.

    Google Scholar 

  8. F. Anceau. The Architecture of Microprocessors. Addison-Wesley, Workingham, 1986.

    Google Scholar 

  9. P. Asahar, S. Devidas, and A. Newton. Sequential Logic Synthesis. Kluwer Academic Publishers, Boston, 1992.

    Google Scholar 

  10. P. Bacchetta, L. Daldos, D. Sciuto, and C. Silvano. Low-power state assignment techniques for finite state machines. In Proc. of the IEEE Inter. Symp. on Circuits and Systems (ISCAS’2000), volume 2, pages 641–644, 2000.

    Google Scholar 

  11. 11. S. I. Baranov. Logic Synthesis of Control Automata. Kluwer Academic Publishers, 1994.

    Google Scholar 

  12. S. I. Baranov and V.A. Skljarov. Digital Units on Programmable LSI with Matrix Structure. Radio i Swiaz, 1986.

    Google Scholar 

  13. A. A. Barkalov. Development of formalized methods of structure synthesis for compositional automata. PhD thesis, Donetsk: DonSTU, 1994. (in Russian).

    Google Scholar 

  14. A. A. Barkalov. Principles of optimization of logic circuit of Moore FSM. Cybernetics and System Analysis, (1):65–72, 1998. (in Russian).

    Google Scholar 

  15. A. A. Barkalov. Synthesis of Control Units with PLD. Donetsk National Technical University, 2002. (in Russian).

    Google Scholar 

  16. A. A. Barkalov and A.A. Barkalov. Design of {M}ealy finite-state machines with transformation of object codes. Inter. Journal "Applied Mathematics and Computer Science", 15(1):151–158, 2005.

    MATH  MathSciNet  Google Scholar 

  17. A. A. Barkalov and A. V. Palagin. Synthesis of Microprogram Control Units. IC NAS of Ukraine, Kiev, 1997. (in Russian).

    Google Scholar 

  18. 18. A. A. Barkalov, M. W馲zyn, and R. Wi\’sniewski. Partial reconfiguration of compositional microprogram control units implemented on fpgas. In Proceedings of IFAC Workshop on Programmable Devices and Embedded Systems (Brno), pages 116–119, 2006.

    Google Scholar 

  19. M. Bolton. Digital System Design with Programmable Logic. Addison-Wesley, Boston, 1990.

    Google Scholar 

  20. B.W. Bomar. Implementation of microprogrammed control in {FPGA}s. IEEE Transactions on Industrial Electronics, 49(2):415–422, 2002.

    Article  Google Scholar 

  21. R. Brayton, G. Hatchel, C.McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston, 1984.

    Google Scholar 

  22. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. MIS: a multi- level logic optimization system. IEEE Transactions on Computer-Aided Design, 6:1062–1081, 1987.

    Article  Google Scholar 

  23. 23. S. Brown and Z. Vernesic. Fundamentals of Digital Logic with {VHDL Design}. McGraw–Hill, 2000.

    Google Scholar 

  24. 24. S. Brown and Z. Vernesic. Fundamentals of Digital Logic with Verilog Design. McGraw–Hill, 2003.

    Google Scholar 

  25. C. Webb C and J. Liptay. A high-frequency custom cmos s/390 microprocessor. IBM Journal of research and Development, 41(4/5):463–473, 1997.

    Article  Google Scholar 

  26. C. Cao, B. O’Nils, and D. Oelmann. A tool for low-power synthesis of {FSM}s with mixed synchronous/asynchronous state memory. In Proc. of Norchip Conf., pages 199–202, 2004.

    Google Scholar 

  27. S. Chattopadhyay. Area conscious state assignment with flip-flop and output polarity selection for finite state machines synthesis – a genetic algorithm. The Computer Journal, 48(4):443–450, 2005.

    Article  MathSciNet  Google Scholar 

  28. 28. S. Chattopadhyay and P. Chaudhuri. Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machines synthesis. In Proc. of the IEEE Inter. Conf. on VLSI Design, pages 522–527, Los Alamitos, 1998. IEEE Computer Society.

    Google Scholar 

  29. 29. Y. C. Chu. Computer Organization and Microprogramming. Prentice Hall, 1972.

    Google Scholar 

  30. M. Ciesielski and S. Jang. {PLADE}: a two-stage {PLA} decomposition. IEEE Transactions on Computer-Aided Design, 11(8), 1992.

    Google Scholar 

  31. 31. R. Czerwinski and D. Kania. State assignment method for high speed {FSM}. In Proc. of Programmable Devices and Systems\/ \cite{Czerw04}, pages 216–221.

    Google Scholar 

  32. 32. R. Czerwinski and D. Kania. State assignment method for high speed {FSM}. In Proc. of Programmable Devices and Systems\/ \cite{Czerw04}, pages 216–221.

    Google Scholar 

  33. R. Czerwinski and D. Kania. State assignment method for high speed {FSM}. In Proc. of Programmable Devices and Systems, pages 216–221, 2004.

    Google Scholar 

  34. D. Debnath and T. Sasao. Multiple-valued minimization to optimize PLA with output EXOR gates. In Proc. of IEEE Inter. Symp. on Mupltiple-Valued Logic, pages 99–104, 1999.

    Google Scholar 

  35. Sasao T. Debnath D. Doutput phase optimization for and-or-exor plas with decoders and its application to design of adders. IFICE Transactions on Information and Systems, E88-D(7):1492–1500, 2005.

    Article  Google Scholar 

  36. S. Deniziak and K. Sapiecha. An efficient algorithm of perfect state encoding for cpld based systems. In Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS’98), pages 47–53, 1998.

    Google Scholar 

  37. S. Devadas and H. Ma. Easily testable {PLA}-based finite state machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(6):604–611, 1990.

    Article  Google Scholar 

  38. S. Devadas, H. Ma, A. Newton, and A. Sangiovanni-Vincentelli. MUSTANG: State assignment of finite state machines targeting multilevel logic implementation. IEEE Transactions on Computer-Aided Design, 7(12):1290–1300, 1988.

    Article  Google Scholar 

  39. S. Devadas and A. Newton. Exact algorithms for output encoding, state assignment, and four-level boolean minimization. IEEE Transactions on Computer-Aided Design, 10(1):143–154, 1991.

    Google Scholar 

  40. X. Du, G. Hachtel, B. Lin, and A. Newton. MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 10(1):28–38, 1991.

    Google Scholar 

  41. B. Escherman. State assignment for hardwired vlsi control units. ACM Computing Surveys, 25(4):415–436, 1993.

    Article  Google Scholar 

  42. S. Goren and F. Ferguson. CHESMIN: a heuristic for state reduction of incompletely specified finite state machines. In Proc. of the Design, Automation and Test in Europe Conf. and Exhibition (DATE’02), pages 248–254, 2002.

    Google Scholar 

  43. B. Gupta, H. Narayanan, and M. Desai. A state assignment scheme targeting performance and area. In Proc. of 12th Inter. Conf. On VLSI Design, pages 378–383, 1999.

    Google Scholar 

  44. S. Habib. Microprogramming and Firmware Engineering Methods. John Wiley and Sons, New York, 1988.

    Google Scholar 

  45. S. Hassoun and T. Sasao. Logic synthesis and verification. Kluwer Academic Publishers, 2002.

    Google Scholar 

  46. Logic synthesis and verification algorithms. Kluwer Academic Publishers, 2000.

    Google Scholar 

  47. E. Hrynkiewicz and D. Kania. Impact of decomposition direction on synthesis effectiveness. In Proc. of Programmable Devices and Systems(PDS’03), pages 144–149, 2003.

    Google Scholar 

  48. H. Hu, H. Xue, and J. Bian. A heuristic state assignment algorithm targeting area. In Proc. of 5th Inter. Conf. on ASIC, volume 1, pages 93–96, 2003.

    Google Scholar 

  49. J. Huang, J. Jou, and W. Shen. ALTO: An iterative area/performance algorithms for LUT-based FPGA technology mapping. IEEE Transactions on VLSI Systems, 18(4):392–400, 2000.

    Article  Google Scholar 

  50. S. Husson. Microprogramming: Principles and Practices. Prentice Hall, Englewood Cliffs, NY, 1970.

    Google Scholar 

  51. A. Iranli, P. Rezvani, and M. Pedram. Low power synthesis of finite state machines with mixed D and T flip-flops. In Proc. of the Asia and South Pacific– DAC, pages 803–808, 2003.

    Google Scholar 

  52. Proc. 11th Conf. Mixed Design of Integrated Circuits and Systems, MIXDES 2004, pages 12–18, Szczecin, Poland, 2004. Departament of Microelectronics and Computer Science, Technical University of Łódźz.

    Google Scholar 

  53. J. Jenkins. Design with FPGAs and CPLDs. Prentice Hall, New York, 1995.

    Google Scholar 

  54. M. J.Flynn and R.F. Rosin. Microprogramming: An introduction and a viewpoint. IEEE transactions on Computers, C–20(7):727–731, 1971.

    Google Scholar 

  55. T. Kam, T. Villa, R. Brayton, and A. Sangiovanni-Vincentelli. A Synthesis of Finie State Machines: Functional Optimization. Kluwer Academic Publishers, Boston, 1998.

    Google Scholar 

  56. D. Kania. Two-level logic synthesis on PAL-based CPLD and {FPGA} using decomposition. In Proc. of 25th Euromicro Conference, pages 278–281, 1999.

    Google Scholar 

  57. D. Kania. Two-level logic synthesis on PALs. Electronic Letters, (17):879–880, 1999.

    Article  Google Scholar 

  58. D. Kania. Coding capacity of PAL-based logic blocks included in CPLDs and FPGAs. In Proc. of IFAC Workshop on Programmable Devices and Sysytems (PDS’2000), pages 164–169. Elseveir Science, 2000.

    Google Scholar 

  59. D. Kania. Decomposition-based synthesis and its application in PAL-oriented technology mapping. In Proc. of 26-th Euromicro Conference, pages 138–145. Maastricht: IEEE Compuetr Society Press, 2000.

    Google Scholar 

  60. D. Kania. An efficient algorithm for output coding in PAL-based {CPLD}s. International Journal of Engineering, 15(4):325–328, 2002.

    Google Scholar 

  61. D. Kania. Logic synthesis of multi–output functions for PAL–based CPLDs. In Proc. of IEEE Inter. Conf. on Field-Programmable Technology, pages 429–432, 2002.

    Google Scholar 

  62. D. Kania. An efficient approach to synthesis of multi-output boolean functions on PAL-based devices. In IEEE Proc. – Computer and Digital Techniques, volume 150, pages 143–149, 2003.

    Article  Google Scholar 

  63. D. Kania. Logic synthesis for PAL-oriented programmable structures. Zeszyty naukowe Politechniki ’Slk a skiej, Gliwice, 2004. (in Polish).

    Google Scholar 

  64. T. Łuba, K. Jasi’nski, and B. Zbierzchowski. Spcialized digital circuits in PLD i FPGA structures. Wydawnictwo Komunikacji i Łaczno’sci, 1997. (in Polish).

    Google Scholar 

  65. C. Maxfield. The Design Warrior’s Guide to FPGAs. Academic Press, Inc., Orlando, FL, USA, 2004.

    Google Scholar 

  66. E. McCluskey. Logic Design Principles. Prentice Hall, Englewood Cliffs, 1986.

    Google Scholar 

  67. G. De Micheli. Symbolic design of combinational and sequential logic implemented by two–level macros. IEEE Transactions on Computer-Aided Design, 5(9):597–616, 1986.

    Article  Google Scholar 

  68. Synthesis and Optimization of Digital Circuits. McGraw–Hill, 1994.

    Google Scholar 

  69. S. Park, S. Yang, and S. Cho. Optimal state assignment technique for partial scan designs. Electronic Letters, (18):1527–1529, 2000.

    Google Scholar 

  70. D. Patterson and J. Henessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Caufmann, San Moteo, CA, 1998.

    Google Scholar 

  71. C. Pedram and A. Despain. Low-power state assignment targeting two- and multilevel logic implementations,volume 17. 1998.

    Google Scholar 

  72. V. Pedroni. Circuit Design with VHDL. MIT Press, Cambridge, 2004.

    Google Scholar 

  73. I. Pomerancz and K. Cheng. STOIC: state assignment based on output/input functions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System, 12(8):1123–1131, 1993.

    Article  Google Scholar 

  74. E. Pugh, L. Johnson, and J. Palmer. IBM’s 360 and Early 370 Systems. MIT Press, Cambridge, MA, 1991.

    Google Scholar 

  75. M. Rawski, T. Luba, Z.Jachna, and P.Tomaszewicz. Design of Embedded Control Systems, chapter The influence of functional decomposition on modern digital design process, pages 193–203. Springer, Boston, 2005.

    Google Scholar 

  76. M. Rawski, H. Selvaraj, and T. Luba. An application of functional decomposition in ROM-based FSM implementation in FPGA devices. Journal of System Architecture, 51(6-7):423–434, 2005.

    Google Scholar 

  77. J. Rho, F. Hatchel, R. Somenzi, and R. Jacoby. Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Transactions on Computer-Aided Design, 13(2):167–177, 1994.

    Article  Google Scholar 

  78. R. Rudell and A. Sangiovanni-Vincentelli. Multiple-valued minimization for pla optimization. IEEE Transactions on Computer-Aided Design, 6(5):727–750,1987.

    Article  Google Scholar 

  79. K. Sakamura. Future SoC possibilities. IEEE Micro., (5):7, 2002.

    Article  Google Scholar 

  80. Z. Salcic. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization. Kluwer Academic Publishers, 1998.

    Google Scholar 

  81. T. Sasao. Input variable assignment and output phase optimization of pla optimization. IEEE Transactions on Computers, 33(10):879–894, 1984.

    Article  MATH  MathSciNet  Google Scholar 

  82. T. Sasao. Switching Theory for Logic Synthesis. Kluwer Academic Publishers, 1999.

    Google Scholar 

  83. G. Saucier, M. Depaulet, and P. Sicard. Asyl: a rule-based system for controller synthesis. IEEE Transactions on Computer-Aided Design, 6(11):1088–1098, 1987.

    Article  Google Scholar 

  84. G.Saucier, P. Sicard, and L. Bouchet. Multi-level synthesis on programmable devices in the ASYL system. In Proceedings of Euro ASIC, pages 136–141, 1990.

    Google Scholar 

  85. C. Scholl. Functional Decomposition with Application to FPGA Synthesis. Kluwer Academic Publishers, Boston, 2001.

    Google Scholar 

  86. S. Schwartz. An algorithm for minimizing read-only memories for machine control. IEEE 10th Annual Symposium on Switching and Automata Theory, pages 28–33, 1968.

    Google Scholar 

  87. E. Sentowich, K. Singh, L. Lavango, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Bryton, and A. Sangiovanni-Vincentelli. SIS: a system for sequential circuit synthesis. Technical report, University of California, Berkely, 1992.

    Google Scholar 

  88. E. Sentowich, K. Singh, L. Lavango, C. Moon, R. Murgai, S. Saldanha, H. Savoj, P. Stephan, R. Bryton, and A. Sangiovanni-Vincentelli. SIS: a system for sequential circuit synthesis. In Proc. of the Inter. Conf. of Computer Design (ICCD’92), pages 328–333, 1992.

    Google Scholar 

  89. B. Shriver and B. Smith. The anatomy of a High-performance Microprocessor: A Systems Perspective. IEEE Computer Society Press, Los Alamitos, CA, 1998.

    Google Scholar 

  90. V. A. Skljarov. Synthesis of automata on matrix LSI. Nauka i Technika, Minsk, 1984. (in Russian).

    Google Scholar 

  91. V. Solovjev and M. Czyzy. Refined CPLD macrocells architecture for effective FSM implementation. In Proc. of the 25th EUROMICRO Conference, volume 1, pages 102–109, Milan, Italy, 1999.

    Google Scholar 

  92. V. Solovjev and M. Czyzy. The universal algorithm for fitting targeted unit to complex programmable logic devices. In Proc. of the 25th EUROMICRO Conference, volume 1, pages 286–289, Milan, Italy, 1999.

    Google Scholar 

  93. V. Solovjev and M. Czyzy. Synthesis of sequential circuits on programmable logic devices based on new models of finite state machines. In Proceedings of the EUROMICRO Conference, Milan, pages 170–173, 2001.

    Google Scholar 

  94. V. V. Solovjev. Design of Digital Systems Using the Programmable Logic Integrated Circuits. Hot line – Telecom, Moscow, 2001. (in Russian).

    Google Scholar 

  95. S. Tucker. Microprogram control for system/360. IBM System Journal, 6(4):222–241, 1967.

    Article  Google Scholar 

  96. G. Venkatamaran, S. Reddy, and I. Pomerancz. GALLOP: genetic algorithm based low power fsm synthesis by simultaneous partitioning and state assignment. In Proc. of 16th Inter. Conf. on VLSI Design, pages 533–538, 2003.

    Google Scholar 

  97. T. Villa, T. Kam, R. Brayton, and A. Sangiovanni-Vincentelli. A Synthesis of Finie State Machines: Logic Optimization. Kluwer Academic Publishers, Boston, 1998.

    Google Scholar 

  98. T. Villa, T. Saldachna, R. Brayton, and A. Sangiovanni-Vincentelli. Symbolic two-level minimization. IEEE Transactions on Computer-Aided Desig, 16(7):692–708, 1997.

    Article  Google Scholar 

  99. T. Villa and A. Sangiovanni-Vincentelli. NOVA: State assignment of finite state machines for optimal two-level logic implememntation. IEEE Transactions on Computer-Aided Design, 9(9):905–924, 1990.

    Article  Google Scholar 

  100. 102. M. Wilkes. The best way to design an automatic calculating machine. In Proc. of Manchester University Computer Inaugural Conference, 1951.

    Google Scholar 

  101. M. Wilkes and J. Stringer. Microprogramming and the design of the control circuits in an electronic digital computer. In Proc. of Cambridge Philosophical Society, volume 49, pages 230–238, 1953.

    Article  MATH  MathSciNet  Google Scholar 

  102. Y. Xia and A. Almani. Genetic algorithm based state assignment for power and area optimization. volume 149, pages 128–133, 2002.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2008 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Barkalov, A., Titarenko, L. (2008). Synthesis of control units with field-programmable logic devices. In: Barkalov, A., Titarenko, L. (eds) Logic Synthesis for Compositional Microprogram Control Units. Lecture Notes Electrical Engineering, vol 22. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-69285-0_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-69285-0_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-69283-6

  • Online ISBN: 978-3-540-69285-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics