Auszug
Im Folgenden werden einige Optimierungsprobleme im Zusammenhang mit der Ablaufplanung untersucht, die Komplexität dieser Probleme analysiert und dann Algorithmen zu deren Lösung vorgestellt. Zunächst werden Ablaufplanungsprobleme nach unterschiedlichen Gesichtspunkten klassifiziert.
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4.8 Literaturhinweise, Ausblicke und Werkzeuge
Adam, T. L., K. M. Chandy und J. R. DICKSON: A Comparison of List Schedules for Parallel Processing Systems. Communication of the ACM, 17(12):685–690, Dezember 1974.
AG, TTTech: TTP-Time-Triggered Protocol. http://www.tttech.com/.
Bachmann, A., M. Schöbinger und L. Thiele: Synthesis of Domain Specific Multiprocessor Systems Including Memory Design. In: VLSI Signal Processing VI, Seiten 417–425, IEEE Press, New York, 1993.
Buttazzo, G.: Rate Monotonic vs. EDF: Judgment Day. In: Proc. of the 3rd Workshop on Embedded Software (EMSOFT), Philadelphia (PA), U.S.A., Oktober 2003.
Buttazzo, G.: Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications. Springer, New York, 2004.
Cia — Can in Automation: TTCAN-Time-Triggered Controller Area Network. http://www.can-cia.de/can/ttcan/.
Coffman, E. G.: Computer and Job-Scheduling Theory. John Wiley and Sons, New York, 1976.
Commoner, F. und A. W. Holt: Marked Directed Graphs. Journal of Computer and System Sciences, 5:511–523, 1971.
Davidson, S., D. Landskov, B. D. Shriver und P. W. Mallett: Some Experiments in Local Microcode Compaction for Horizontal Machines. IEEE Trans. on Computers, C-30(7):460–477, 1981.
ETAS: ERCOSek, OSEK based Real-Time Operating System. http://www.etas.de/html/en/products/ec/ercosek/en_products_ec_ercosek_index.htm.
ETAS: Real-Time Architect. http://www.livedevices.co.uk/realtime.shtml.
Fettweis, A.: Realizability of Digital Filter Networks. Archiv Elek. Übertragung, 30(2):90–96, 1976.
Fisher, J.: Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trans. on Computers, C-30(7):478–490, Juli 1981.
Flexray-Group: FlexRay. http://www.flexray.com.
Garey, M. R. und D. S. Johnson: Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, New York, 1979.
Gebotys, C. und M. I. Elmasry: Global optimization Approach for Architectural Synthesis. IEEE Journal on CAD, 12(9):1266–1278, September 1993.
Girczyc, E.: Loop Winding-A Data Flow Approach to Functional Pipelining. In: Proc. ISCAS, Seiten 382–285, Philadelphia, PA, 1987.
Goossens, G., J. Rabaey, J. Vandewalle und H. De Man: An Efficient Microcode Compiler for Custom Microprocessor DSP Systems. In: Proc. of the Int. Conf. on CAD, Seiten 24–27, San Jose, CA, 1987.
Hafer, L. und A. C. Parker: A Formal Method for the Specification, Analysis and Design of Register-Transfer Digital Logic. IEEE Trans. on Computer-Aided Design, CAD-2:4–18, 1983.
Hillier, F. S. und G. J. Lieberman:An Introduction to Operations Research. Holden Day, San Francisco, 2005. 8. Auflage.
Horowitz, J.: Critical Path Scheduling, Management Control Through CPM and PERT. R. E. Krieger, Huntington, New York, 1980.
Hu, T. C.: Parallel Sequencing and Assembly Line Problems. Operations Research, 9(6):841–848, 1961.
Hwang, C. T., J. H. Lee und Y. C. Hsu: A Formal Approach to the Scheduling Problem in High Level Synthesis. IEEE Trans. on Computer-Aided Design, CAD-10(4):464–475, April 1991.
Kaneshiro, R., K. Konstantinides und J. Tani: Task Allocation and Scheduling Models for Multiprocessor Digital Signal Processing. IEEE Trans. on Accoustics, Speech and Signal Processing, 38(12):2151–2161, Dezember 1990.
Klein, M.: A Practitioner’s Handbook for Real-Time Analysis. Kluwer Academic Publishers, Boston, Massachusetts, U.S.A., 1993.
Kopetz, H.: Real-Time Systems — Design Principles for Distributed Embedded Applications. Kluwer Academic Publishers, Boston, Massachusetts, 1997.
Lee, E. A.: A Coupled Hardware and Software Architecture for Programmable Digital Signal Processors. Doktorarbeit, Dept. of EECS, UC Berkeley, Berkeley, CA 94720, U.S.A., 1986.
Leiserson, C. E., F. M. Rose und J. B. Saxe: Optimizing Synchronous Circuitry by Retiming. In: Proc. Third Caltech Conf. on VLSI, Seiten 87–116, Rockville, MD, 1983.
Liu, J.: Real-Time Systems. Prentice-Hall, Boston, Massachusetts, U.S.A., 2000.
Lucke, L. F. und K. K. Parhi: Generalized ILP Scheduling and Allocation for High-Level DSP Synthesis. In: Proc. IEEE Custom Integr. Circuits Conference, Seiten 11–20, 1993.
Pangrle, B. und D. Gajski: Design Tools for Intelligent Silicon Compilation. IEEE Trans. on CAD, CAD-6(6):1098–1112, November 1987.
Parhi, K. K. und D. G. Messerschmitt: Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding. IEEE Trans. on Computers, 40(2):178–194, Februar 1991.
Park, N. und A. C. Parker: Sehwa: A Software Package for Synthesis of Pipelines from Behavioral Specifications. IEEE Trans. on CAD/ICAS, CAD-7(3):356–370, 1988.
Paulin, P. G. und J. P. Knight: Force-Directed Scheduling for the Behavioral Synthesis. IEEE Trans. on Computer-Aided Design, CAD-8(6):661–679, Juli 1989.
Philips Semiconductors: Controller Area Network CAN. http://www.semiconductors.philips.com/can/.
Pop, T., P. Eles und Z. Peng: Holistic Scheduling and Analysis of Mixed Time/Event-Triggered Distributed Embedded Systems. In: Proc. of the International Symposium on Hardware/Software Codesign, Seiten 187–192, Estes Park, U.S.A., 2002.
Prakash, S. und A. C. Parker: SOS: Synthesis of Application-Specific Heterogeneous Multiprocessor Systems. Journal Parallel and Distributed Computing, 16:338–351, 1992.
Rao, S. K.: Regular Iterative Algorithms and Their Implementations on Processor Arrays. Doktorarbeit, Stanford University, CA, 1985.
Renfors, M. und Y. neuvo: The Maximum Sampling Rate of Digital Filters Under Hardware Speed Constraints. IEEE Trans. on Circuits and Systems, 28(3):196–202, März 1981.
Richter, K.: Compositional Scheduling Analysis Using Standard Event Models. Doktorarbeit, Technische Universität Braunschweig, Deutschland, 2004.
Schwartz, D. A. und III T. P. Barnwell: Cyclo-Static Solutions: Optimal Multiprocessor Realizations of Recursive Algorithms. In: VLSI Signal Processing II, Seiten 117–128, IEEE Press, 1986.
Stankovic, J., M. Spuri, K. Ramamritham und G. Buttazzo:Deadline Scheduling for Real-Time Systems — EDF and Related Algorithms. Kluwer Academic Publishers, Boston, Massachusetts, U.S.A., 1998.
Symtavision: SymTA/S Tool Suite, 2006. http://www.symtavision.com/downloads/System_Level_Performance_Analysis-the_SymTA-S_Approach.pdf.
Teich, J.: A Compiler for Application-Specific Processor Arrays. Shaker (Reihe Elektrotechnik). Zugl. Saarbrücken, Univ. Diss, ISBN 3-86111-701-0, Aachen, Germany, 1993.
Teich, J. und L. Thiele: Control Generation in the Design of Processor Arrays. Int. Journal on VLSI and Signal Processing, 3(2):77–92, 1991.
Teich, J. und L. Thiele: Partitioning of Processor Arrays: A Piecewise Regular Approach. INTEGRATION: The VLSI Journal, 14(3):297–332, 1993.
Teich, J., L. Thiele und L. Zhang: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. In: ASAP96-Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors, Seiten 131–144, Chicago, U.S.A., August 1996.
Thiele, L., S. Chakraborty und M. Naedele: Real-Time Calculus for Scheduling Hard Real-Time Systems. In: Proc. International Symposium on Circuits and Systems, Seiten 101–104, Geneva, Switzerland, 2000.
Tindell, K.: Adding Time-Offsets to Schedulability Analysis. Technischer Bericht, Department of Computer Science, University of York, UK, 1994.
Tindell, K. und J. Clark: Holistic Schedulability Analysis for Distributed Realtime Systems. Microprocessing and Microprogramming-Euromicro Journal (Special Issue on Parallel Embedded Real-Time Systems), 40:117–134, 1994.
Tindell, K., J. Clark und A. Wellings: Analysing Real-Time Communications: Controller Area Network. In: Proc. of the International Real-Time Systems Symposium, Seiten 259–263, San Juan, Puerto Rico, 1994.
Tri-Pacific Software, Inc.: RAPID RMA. http://www.tripac.com/html/prod-fact-rrm.html.
TTTech AG: TTP Software Development Suite. http://www.tttech.com/products/software/ttptools/overview.htm.
Vast Systems Technology Corporation: CoMET — Electronic System-level Design Environment. http://www.vastsystems.com/products comet.html.
Vector Informatik GmbH: CANAlyzer — The Tool for Comprehensive Network Analysis. http://www.canalyzer.com.
Verhaegh, W. F., P. E. Lippens, E. H. Aarts, J. H. Korst und J. L. Vanmeerbergen: Improved Force-Directed Scheduling in High-Throughput Digital Signal Processing. IEEE Trans. on CAD, 14(8):945–960, August 1995.
Volcano Communications Technologies AB: Volcano Network Architect for CAN. http://www.volcanoautomotive.com/products/can.htm.
Xu, J. und D. L. Parnas: Priority Scheduling versus Pre-Run-Time Scheduling. Real-Time Systems, 18(1):7–24, 2000.
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(2007). Ablaufplanung. In: Digitale Hardware/Software-Systeme. eXamen.press. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-46824-0_4
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