Chapter

Cryptographic Hardware and Embedded Systems - CHES 2003

Volume 2779 of the series Lecture Notes in Computer Science pp 137-151

Security Evaluation of Asynchronous Circuits

  • Jacques J. A. FournierAffiliated withSecurity Technologies Department, Gemplus
  • , Simon MooreAffiliated withComputer Laboratory, University of Cambridge
  • , Huiyun LiAffiliated withComputer Laboratory, University of Cambridge
  • , Robert MullinsAffiliated withComputer Laboratory, University of Cambridge
  • , George TaylorAffiliated withComputer Laboratory, University of Cambridge

Abstract

Balanced asynchronous circuits have been touted as a superior replacement for conventional synchronous circuits. To assess these claims, we have designed, manufactured and tested an experimental asynchronous smart-card style device. In this paper we describe the tests performed and show that asynchronous circuits can provide better tamper-resistance. However, we have also discovered weaknesses with our test chip, some of which have resulted in new designs, and others which are more fundamental to the asynchronous design approach. This has led us to investigate the novel approach of design-time security analysis rather than rely on post manufacture analysis.

Keywords

Asynchronous circuits Dual-Rail encoding Power Analysis EMA Fault Analysis Design-time security evaluation