Abstract
It takes about four to five weeks to fabricate a semiconductor memory device. As the fabrication process consists of various operations, there is a possibility of fabricating a final product with defects. It would be impossible for us to repair a memory device if it has numerous defects that cannot be dealt with properly. However, in case of a small number of defects, it is desirable to reuse a defective die (standard unit measuring a device on a wafer) after repair rather than to discard it, because reuse is an essential element for memory device manufactures to cut costs effectively. To perform the reuse, laser-repair process and redundancy analysis for setting an accurate target in the laser-repair process is needed. In this paper, cost reduction was attempted by reducing time in carrying out a new type of redundancy analysis, after simulating each defect.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Memories and redundancy techniques in IEEE ISSCC Dig. Tech. Papers, pp. 80–87 (1981)
Day, J.R.: A fault-driven comprehensive redundancy algorithm for repair of dynamic RAMs. IEEE Design & Test 2(3), 33–44 (1985)
Kuo, S.-Y., Fuchs, W.K.: Efficient spare allocation in reconfigurable arrays. IEEE Design & Test 4, 24–31 (1987)
Tarr, M., Boudreau, D., Murphy, R.: Defect Analysis System Speeds Test and Repair of Redundant Memories. Electronics, p. 175, January 12 (1984)
Day, J.R.: A Fault-Driven Comprehensive Redundancy Algorithm. IEEE Design & Test 2(3), 35–44 (1985)
Lombardi, F., Huang, W.K.: Approaches for the repair of VLSI/WSI RRAMs by Row/Column deletion. In: Proc. 18th Int. Symp. on Fault-Tolerant Computing, July 1988, pp. 342–347 (1988)
Huang, W.K., Shen, Y.N., Lombardi, F.: New Approaches for the Repairs of Memories with Redundancy by Row/ Column Deletion for Yield Enhancement. Transactions on Computer-Aided Design 9(3) (March 1990)
Law, A.M., David Kelton, W.: Simulation Modeling and Analysis, 3rd edn., ch. 4, pp. 235–260 (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Han, Y., Lee, C. (2004). RRAM Spare Allocation in Semiconductor Manufacturing for Yield Improvement. In: Negoita, M.G., Howlett, R.J., Jain, L.C. (eds) Knowledge-Based Intelligent Information and Engineering Systems. KES 2004. Lecture Notes in Computer Science(), vol 3215. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30134-9_14
Download citation
DOI: https://doi.org/10.1007/978-3-540-30134-9_14
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23205-6
Online ISBN: 978-3-540-30134-9
eBook Packages: Springer Book Archive